riscv/rocket-chip
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Fix the SCR file for Chisel 3

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This commit is contained in:
Palmer Dabbelt 2016-03-05 17:20:25 -08:00
parent b5992186df
commit c989ec5813
2 changed files with 3 additions and 3 deletions
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4
src/main/scala/RocketChip.scala
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@ -176,8 +176,8 @@ class Uncore(implicit val p: Parameters) extends Module
scrArb.io.in(0) <> htif.io.scr
scrArb.io.in(1) <> outmemsys.io.scr
scrFile.io.smi <> scrArb.io.out
scrFile.io.scr.attach(UInt(nTiles), "N_CORES", false, true)
scrFile.io.scr.attach(UInt(p(MMIOBase) >> 20), "MMIO_BASE", false, true)
scrFile.io.scr.attach(Wire(init = UInt(nTiles)), "N_CORES")
scrFile.io.scr.attach(Wire(init = UInt(p(MMIOBase) >> 20)), "MMIO_BASE")
// scrFile.io.scr <> (... your SCR connections ...)
// Configures the enabled memory channels. This can't be changed while the

2
uncore

@ -1 +1 @@
Subproject commit 9d4a38e955a1ea8b2bd88dd599e3ffdebaf2b78c
Subproject commit fa6be954e150e5a3d64e8221b6083c9feaed4268