diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index fa943da6..5abb5073 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -176,8 +176,8 @@ class Uncore(implicit val p: Parameters) extends Module
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr
   scrFile.io.smi <> scrArb.io.out
-  scrFile.io.scr.attach(UInt(nTiles), "N_CORES", false, true)
-  scrFile.io.scr.attach(UInt(p(MMIOBase) >> 20), "MMIO_BASE", false, true)
+  scrFile.io.scr.attach(Wire(init = UInt(nTiles)), "N_CORES")
+  scrFile.io.scr.attach(Wire(init = UInt(p(MMIOBase) >> 20)), "MMIO_BASE")
   // scrFile.io.scr <> (... your SCR connections ...)
 
   // Configures the enabled memory channels.  This can't be changed while the
diff --git a/uncore b/uncore
index 9d4a38e9..fa6be954 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 9d4a38e955a1ea8b2bd88dd599e3ffdebaf2b78c
+Subproject commit fa6be954e150e5a3d64e8221b6083c9feaed4268