Merge pull request #932 from freechipsproject/tl-bus-delayer
tilelink: allow insertion of TLDelayer on TLBus outward node
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commit
c8f8806df0
@ -39,6 +39,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
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// TileLink connection global parameters
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case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
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case TLCombinationalCheck => false
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case TLBusDelayProbability => 0.0
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})
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/* Composable partial function Configs to set individual parameters */
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@ -44,6 +44,8 @@ case object MemoryBusParams extends Field[MemoryBusParams]
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/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
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class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) {
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xbar.suggestName("MemoryBus")
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def fromCoherenceManager: TLInwardNode = inwardBufNode
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def toDRAMController: TLOutwardNode = outwardBufNode
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def toVariableWidthSlave: TLOutwardNode = outwardFragNode
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@ -22,6 +22,8 @@ case class PeripheryBusParams(
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case object PeripheryBusParams extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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xbar.suggestName("PeripheryBus")
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def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
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TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
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}
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@ -18,6 +18,8 @@ case class SystemBusParams(
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case object SystemBusParams extends Field[SystemBusParams]
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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xbar.suggestName("SystemBus")
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private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
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inwardNode :=* master_splitter.node
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def busView = master_splitter.node.edgesIn.head
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@ -3,9 +3,10 @@
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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case object TLBusDelayProbability extends Field[Double]
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/** Specifies widths of various attachement points in the SoC */
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trait TLBusParams {
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@ -26,19 +27,32 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
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val masterBuffering = params.masterBuffering
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val slaveBuffering = params.slaveBuffering
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require(blockBytes % beatBytes == 0)
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private val delayProb = p(TLBusDelayProbability)
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private val xbar = LazyModule(new TLXbar)
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protected val xbar = LazyModule(new TLXbar)
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private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
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private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
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private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
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private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
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private val delayedNode = if (delayProb > 0.0) {
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val firstDelay = LazyModule(new TLDelayer(delayProb))
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val flowDelay = LazyModule(new TLBuffer(BufferParams.flow))
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val secondDelay = LazyModule(new TLDelayer(delayProb))
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firstDelay.node :*= xbar.node
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flowDelay.node :*= firstDelay.node
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secondDelay.node :*= flowDelay.node
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secondDelay.node
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} else {
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xbar.node
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}
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xbar.node :=* master_buffer.node
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slave_buffer.node :*= xbar.node
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slave_buffer.node :*= delayedNode
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slave_frag.node :*= slave_buffer.node
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slave_ww.node :*= slave_buffer.node
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protected def outwardNode: TLOutwardNode = xbar.node
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protected def outwardNode: TLOutwardNode = delayedNode
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protected def outwardBufNode: TLOutwardNode = slave_buffer.node
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protected def outwardFragNode: TLOutwardNode = slave_frag.node
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protected def outwardWWNode: TLOutwardNode = slave_ww.node
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