From c457c9cb9f7a02bb31276f50280be4a6e248ad87 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 7 Aug 2017 16:43:06 -0700 Subject: [PATCH 1/3] tilelink: allow insertion of TLDelayer on TLBus outward node --- src/main/scala/coreplex/Configs.scala | 1 + src/main/scala/tilelink/Bus.scala | 14 ++++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 3ed5f2bd..710d1f57 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -39,6 +39,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => { // TileLink connection global parameters case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args))) case TLCombinationalCheck => false + case TLBusDelayProbability => 0.0 }) /* Composable partial function Configs to set individual parameters */ diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala index 134a14f7..d3c143ae 100644 --- a/src/main/scala/tilelink/Bus.scala +++ b/src/main/scala/tilelink/Bus.scala @@ -3,9 +3,10 @@ package freechips.rocketchip.tilelink import Chisel._ -import freechips.rocketchip.config.Parameters +import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ + +case object TLBusDelayProbability extends Field[Double] /** Specifies widths of various attachement points in the SoC */ trait TLBusParams { @@ -26,7 +27,9 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends val masterBuffering = params.masterBuffering val slaveBuffering = params.slaveBuffering require(blockBytes % beatBytes == 0) + private val delayProb = p(TLBusDelayProbability) + private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None private val xbar = LazyModule(new TLXbar) private val master_buffer = LazyModule(new TLBuffer(masterBuffering)) private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering)) @@ -34,11 +37,14 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends private val slave_ww = LazyModule(new TLWidthWidget(beatBytes)) xbar.node :=* master_buffer.node - slave_buffer.node :*= xbar.node + slave_buffer.node :*= delayer.map { d => + d.node :*= xbar.node + d.node + } .getOrElse { xbar.node } slave_frag.node :*= slave_buffer.node slave_ww.node :*= slave_buffer.node - protected def outwardNode: TLOutwardNode = xbar.node + protected def outwardNode: TLOutwardNode = delayer.map(_.node).getOrElse(xbar.node) protected def outwardBufNode: TLOutwardNode = slave_buffer.node protected def outwardFragNode: TLOutwardNode = slave_frag.node protected def outwardWWNode: TLOutwardNode = slave_ww.node From 2910d6fa2aa96c046a7db640deaa05002842cd0c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 7 Aug 2017 17:30:24 -0700 Subject: [PATCH 2/3] tilelink: make bus xbar protected so it can be suggestNamed --- src/main/scala/coreplex/MemoryBus.scala | 2 ++ src/main/scala/coreplex/PeripheryBus.scala | 2 ++ src/main/scala/coreplex/SystemBus.scala | 2 ++ src/main/scala/tilelink/Bus.scala | 2 +- 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala index d78cddee..d71507ba 100644 --- a/src/main/scala/coreplex/MemoryBus.scala +++ b/src/main/scala/coreplex/MemoryBus.scala @@ -44,6 +44,8 @@ case object MemoryBusParams extends Field[MemoryBusParams] /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) { + xbar.suggestName("MemoryBus") + def fromCoherenceManager: TLInwardNode = inwardBufNode def toDRAMController: TLOutwardNode = outwardBufNode def toVariableWidthSlave: TLOutwardNode = outwardFragNode diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala index 42352afa..02d098c2 100644 --- a/src/main/scala/coreplex/PeripheryBus.scala +++ b/src/main/scala/coreplex/PeripheryBus.scala @@ -22,6 +22,8 @@ case class PeripheryBusParams( case object PeripheryBusParams extends Field[PeripheryBusParams] class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) { + xbar.suggestName("PeripheryBus") + def toFixedWidthSingleBeatSlave(widthBytes: Int) = { TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode) } diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 9fe8a56b..501bad37 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -18,6 +18,8 @@ case class SystemBusParams( case object SystemBusParams extends Field[SystemBusParams] class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) { + xbar.suggestName("SystemBus") + private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks inwardNode :=* master_splitter.node def busView = master_splitter.node.edgesIn.head diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala index d3c143ae..e2a63cfb 100644 --- a/src/main/scala/tilelink/Bus.scala +++ b/src/main/scala/tilelink/Bus.scala @@ -30,7 +30,7 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends private val delayProb = p(TLBusDelayProbability) private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None - private val xbar = LazyModule(new TLXbar) + protected val xbar = LazyModule(new TLXbar) private val master_buffer = LazyModule(new TLBuffer(masterBuffering)) private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering)) private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes)) From c4092dd0ccbfad77af352d4577f8f01dc2d8a36a Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 7 Aug 2017 17:36:07 -0700 Subject: [PATCH 3/3] tilelink: improve entropy of bus delayer --- src/main/scala/tilelink/Bus.scala | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala index e2a63cfb..9d72ad7c 100644 --- a/src/main/scala/tilelink/Bus.scala +++ b/src/main/scala/tilelink/Bus.scala @@ -29,22 +29,30 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends require(blockBytes % beatBytes == 0) private val delayProb = p(TLBusDelayProbability) - private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None protected val xbar = LazyModule(new TLXbar) private val master_buffer = LazyModule(new TLBuffer(masterBuffering)) private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering)) private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes)) private val slave_ww = LazyModule(new TLWidthWidget(beatBytes)) + private val delayedNode = if (delayProb > 0.0) { + val firstDelay = LazyModule(new TLDelayer(delayProb)) + val flowDelay = LazyModule(new TLBuffer(BufferParams.flow)) + val secondDelay = LazyModule(new TLDelayer(delayProb)) + firstDelay.node :*= xbar.node + flowDelay.node :*= firstDelay.node + secondDelay.node :*= flowDelay.node + secondDelay.node + } else { + xbar.node + } + xbar.node :=* master_buffer.node - slave_buffer.node :*= delayer.map { d => - d.node :*= xbar.node - d.node - } .getOrElse { xbar.node } + slave_buffer.node :*= delayedNode slave_frag.node :*= slave_buffer.node slave_ww.node :*= slave_buffer.node - protected def outwardNode: TLOutwardNode = delayer.map(_.node).getOrElse(xbar.node) + protected def outwardNode: TLOutwardNode = delayedNode protected def outwardBufNode: TLOutwardNode = slave_buffer.node protected def outwardFragNode: TLOutwardNode = slave_frag.node protected def outwardWWNode: TLOutwardNode = slave_ww.node