Merge pull request #932 from freechipsproject/tl-bus-delayer

tilelink: allow insertion of TLDelayer on TLBus outward node

src/main/scala/coreplex/Configs.scala

@@ -39,6 +39,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
   // TileLink connection global parameters
   case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
   case TLCombinationalCheck => false
+  case TLBusDelayProbability => 0.0
 })
 
 /* Composable partial function Configs to set individual parameters */

src/main/scala/coreplex/MemoryBus.scala

@@ -44,6 +44,8 @@ case object MemoryBusParams extends Field[MemoryBusParams]
 
 /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
 class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) {
+  xbar.suggestName("MemoryBus")
+
   def fromCoherenceManager: TLInwardNode = inwardBufNode
   def toDRAMController: TLOutwardNode = outwardBufNode
   def toVariableWidthSlave: TLOutwardNode = outwardFragNode

src/main/scala/coreplex/PeripheryBus.scala

@@ -22,6 +22,8 @@ case class PeripheryBusParams(
 case object PeripheryBusParams extends Field[PeripheryBusParams]
 
 class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
+  xbar.suggestName("PeripheryBus")
+
   def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
     TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
   }

src/main/scala/coreplex/SystemBus.scala

@@ -18,6 +18,8 @@ case class SystemBusParams(
 case object SystemBusParams extends Field[SystemBusParams]
 
 class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
+  xbar.suggestName("SystemBus")
+
   private val master_splitter = LazyModule(new TLSplitter)  // Allows cycle-free connection to external networks
   inwardNode :=* master_splitter.node
   def busView = master_splitter.node.edgesIn.head

src/main/scala/tilelink/Bus.scala

@@ -3,9 +3,10 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
+
+case object TLBusDelayProbability extends Field[Double]
 
 /** Specifies widths of various attachement points in the SoC */
 trait TLBusParams {
@@ -26,19 +27,32 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
   val masterBuffering = params.masterBuffering
   val slaveBuffering = params.slaveBuffering
   require(blockBytes % beatBytes == 0)
+  private val delayProb = p(TLBusDelayProbability)
 
-  private val xbar = LazyModule(new TLXbar)
+  protected val xbar = LazyModule(new TLXbar)
   private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
   private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
   private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
   private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
 
+  private val delayedNode = if (delayProb > 0.0) {
+    val firstDelay = LazyModule(new TLDelayer(delayProb))
+    val flowDelay = LazyModule(new TLBuffer(BufferParams.flow))
+    val secondDelay = LazyModule(new TLDelayer(delayProb))
+    firstDelay.node :*= xbar.node
+    flowDelay.node :*= firstDelay.node
+    secondDelay.node :*= flowDelay.node
+    secondDelay.node
+  } else {
+    xbar.node
+  }
+
   xbar.node :=* master_buffer.node
-  slave_buffer.node :*= xbar.node
+  slave_buffer.node :*= delayedNode
   slave_frag.node :*= slave_buffer.node
   slave_ww.node :*= slave_buffer.node
 
-  protected def outwardNode: TLOutwardNode = xbar.node
+  protected def outwardNode: TLOutwardNode = delayedNode
   protected def outwardBufNode: TLOutwardNode = slave_buffer.node
   protected def outwardFragNode: TLOutwardNode = slave_frag.node
   protected def outwardWWNode: TLOutwardNode = slave_ww.node