riscv/rocket-chip
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Update breakpoint spec

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This commit is contained in:
Andrew Waterman 2016-06-09 19:07:10 -07:00
parent 2c325151bf
commit c8c7246cce
2 changed files with 36 additions and 13 deletions
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23
rocket/src/main/scala/breakpoint.scala
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@ -6,8 +6,20 @@ import Chisel._
import Util._ import Util._
import cde.Parameters import cde.Parameters
class BPControl extends Bundle { class TDRSelect(implicit p: Parameters) extends CoreBundle()(p) {
val matchcond = UInt(width = 2) val tdrmode = Bool()
val reserved = UInt(width = xLen - 1 - log2Up(nTDR))
val tdrindex = UInt(width = log2Up(nTDR))
def nTDR = p(NBreakpoints)
}
class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
val tdrtype = UInt(width = 4)
val bpamaskmax = UInt(width = 5)
val reserved = UInt(width = xLen-28)
val bpaction = UInt(width = 8)
val bpmatch = UInt(width = 4)
val m = Bool() val m = Bool()
val h = Bool() val h = Bool()
val s = Bool() val s = Bool()
@ -15,6 +27,9 @@ class BPControl extends Bundle {
val r = Bool() val r = Bool()
val w = Bool() val w = Bool()
val x = Bool() val x = Bool()
def tdrType = 1
def bpaMaskMax = 4
} }
class BreakpointUnit(implicit p: Parameters) extends CoreModule()(p) { class BreakpointUnit(implicit p: Parameters) extends CoreModule()(p) {
@ -34,8 +49,8 @@ class BreakpointUnit(implicit p: Parameters) extends CoreModule()(p) {
io.xcpt_st := false io.xcpt_st := false
for (((bpc, bpa), i) <- io.bpcontrol zip io.bpaddress zipWithIndex) { for (((bpc, bpa), i) <- io.bpcontrol zip io.bpaddress zipWithIndex) {
var mask: UInt = bpc.matchcond(1) var mask: UInt = bpc.bpmatch(1)
for (i <- 1 until log2Ceil(16)) for (i <- 1 until bpc.bpaMaskMax)
mask = Cat(mask(i-1) && bpa(i-1), mask) mask = Cat(mask(i-1) && bpa(i-1), mask)
def matches(x: UInt) = (~x | mask) === (~bpa | mask) def matches(x: UInt) = (~x | mask) === (~bpa | mask)

26
rocket/src/main/scala/csr.scala
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@ -173,7 +173,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val reg_dpc = Reg(UInt(width = vaddrBitsExtended)) val reg_dpc = Reg(UInt(width = vaddrBitsExtended))
val reg_dscratch = Reg(UInt(width = xLen)) val reg_dscratch = Reg(UInt(width = xLen))
val reg_tdrselect = Reg(init=UInt(0, log2Up(p(NBreakpoints)))) val reg_tdrselect = Reg(new TDRSelect)
val reg_bpcontrol = Reg(Vec(p(NBreakpoints), new BPControl)) val reg_bpcontrol = Reg(Vec(p(NBreakpoints), new BPControl))
val reg_bpaddress = Reg(Vec(p(NBreakpoints), UInt(width = vaddrBits))) val reg_bpaddress = Reg(Vec(p(NBreakpoints), UInt(width = vaddrBits)))
@ -237,9 +237,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val read_mstatus = io.status.toBits()(xLen-1,0) val read_mstatus = io.status.toBits()(xLen-1,0)
val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
CSRs.tdrselect -> reg_tdrselect, CSRs.tdrselect -> reg_tdrselect.toBits,
CSRs.tdrdata1 -> (if (p(NBreakpoints) > 0) reg_bpcontrol(reg_tdrselect).toBits else UInt(0)), CSRs.tdrdata1 -> (if (p(NBreakpoints) > 0) reg_bpcontrol(reg_tdrselect.tdrindex).toBits else UInt(0)),
CSRs.tdrdata2 -> (if (p(NBreakpoints) > 0) reg_bpaddress(reg_tdrselect) else UInt(0)), CSRs.tdrdata2 -> (if (p(NBreakpoints) > 0) reg_bpaddress(reg_tdrselect.tdrindex) else UInt(0)),
CSRs.mimpid -> UInt(0), CSRs.mimpid -> UInt(0),
CSRs.marchid -> UInt(0), CSRs.marchid -> UInt(0),
CSRs.mvendorid -> UInt(0), CSRs.mvendorid -> UInt(0),
@ -525,13 +525,15 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata & delegable_exceptions } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata & delegable_exceptions }
} }
if (p(NBreakpoints) > 0) { if (p(NBreakpoints) > 0) {
when (decoded_addr(CSRs.tdrselect)) { reg_tdrselect := Mux(wdata(log2Up(p(NBreakpoints))-1,0) >= UInt(p(NBreakpoints)), UInt(0), wdata(log2Up(p(NBreakpoints))-1,0)) } val canWrite = reg_tdrselect.tdrmode || reg_debug
when (decoded_addr(CSRs.tdrdata1)) { val newTDR = new TDRSelect().fromBits(wdata)
when (decoded_addr(CSRs.tdrselect) && newTDR.tdrindex < newTDR.nTDR) { reg_tdrselect.tdrindex := newTDR.tdrindex }
when (decoded_addr(CSRs.tdrdata1) && canWrite) {
val newBPC = new BPControl().fromBits(wdata) val newBPC = new BPControl().fromBits(wdata)
reg_bpcontrol(reg_tdrselect) := newBPC reg_bpcontrol(reg_tdrselect.tdrindex) := newBPC
reg_bpcontrol(reg_tdrselect).matchcond := newBPC.matchcond | 1 /* exact/range only */ reg_bpcontrol(reg_tdrselect.tdrindex).bpmatch := newBPC.bpmatch & 2 /* exact/NAPOT only */
} }
when (decoded_addr(CSRs.tdrdata2)) { reg_bpaddress(reg_tdrselect) := wdata } when (decoded_addr(CSRs.tdrdata2) && canWrite) { reg_bpaddress(reg_tdrselect.tdrindex) := wdata }
} }
} }
@ -549,7 +551,13 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
reg_mstatus.mprv := false reg_mstatus.mprv := false
} }
reg_tdrselect.reserved := 0
reg_tdrselect.tdrmode := true // TODO support D-mode breakpoint theft
for (bpc <- reg_bpcontrol) { for (bpc <- reg_bpcontrol) {
bpc.tdrtype := bpc.tdrType
bpc.bpamaskmax := bpc.bpaMaskMax
bpc.reserved := 0
bpc.bpaction := 0
bpc.h := false bpc.h := false
if (!usingVM) bpc.s := false if (!usingVM) bpc.s := false
if (!usingUser) bpc.u := false if (!usingUser) bpc.u := false