riscv/rocket-chip
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Report ITIM uncorrectable errors over D-channel

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This commit is contained in:
Andrew Waterman 2017-11-06 12:32:45 -08:00
parent 7cc7cd5992
commit c84848afa6
1 changed files with 2 additions and 0 deletions
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src/main/scala/rocket/ICache.scala
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@ -312,6 +312,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
} }
respValid := s2_slaveValid || (respValid && !tl.d.ready) respValid := s2_slaveValid || (respValid && !tl.d.ready)
val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable, s2_slaveValid)
when (s2_slaveValid) { when (s2_slaveValid) {
when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true }
def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))
@ -323,6 +324,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
edge_in.get.AccessAck(s1_a), edge_in.get.AccessAck(s1_a),
edge_in.get.AccessAck(s1_a, UInt(0))) edge_in.get.AccessAck(s1_a, UInt(0)))
tl.d.bits.data := s1s3_slaveData tl.d.bits.data := s1s3_slaveData
tl.d.bits.error := respError
// Tie off unused channels // Tie off unused channels
tl.b.valid := false tl.b.valid := false