From c84848afa672a890240c89597198d4c9e4879770 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 6 Nov 2017 12:32:45 -0800 Subject: [PATCH] Report ITIM uncorrectable errors over D-channel --- src/main/scala/rocket/ICache.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 60db666b..40c705d8 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -312,6 +312,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) } respValid := s2_slaveValid || (respValid && !tl.d.ready) + val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable, s2_slaveValid) when (s2_slaveValid) { when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) @@ -323,6 +324,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) edge_in.get.AccessAck(s1_a), edge_in.get.AccessAck(s1_a, UInt(0))) tl.d.bits.data := s1s3_slaveData + tl.d.bits.error := respError // Tie off unused channels tl.b.valid := false