riscv/rocket-chip
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use scala firrtl instead of stanza firrtl

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This commit is contained in:
Howard Mao 2016-03-30 19:35:25 -07:00
parent be612e3843
commit c831a0a4e5
1 changed files with 1 additions and 1 deletions
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vsim/Makefrag-verilog
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@ -18,7 +18,7 @@ else
FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
$(FIRRTL):
$(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build
$(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build-scala
# If I don't mark these as .SECONDARY then make will delete these internal
# files.