From c831a0a4e5d0e1cf6895822fecae5d82a6f9efe7 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 30 Mar 2016 19:35:25 -0700 Subject: [PATCH] use scala firrtl instead of stanza firrtl --- vsim/Makefrag-verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index 66034bc2..65fd4c31 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -18,7 +18,7 @@ else FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl $(FIRRTL): - $(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build + $(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build-scala # If I don't mark these as .SECONDARY then make will delete these internal # files.