riscv/rocket-chip
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rocketchip: remove obsolete TL1 config

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Wesley W. Terpstra committed 2016-11-17 14:24:45 -08:00
1 parent dfc3a0dafb
commit c82b371354
4 files changed
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src/main/scala/rocketchip/Periphery.scala
-2
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@@ -85,8 +85,6 @@ trait HasPeripheryParameters {
lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
lazy val edgeSlaveParams = p.alterPartial({ case TLId => "EdgetoSlave" })
lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
lazy val peripheryBusConfig = p(PeripheryBusConfig)
lazy val socBusConfig = p(SOCBusConfig)
lazy val cacheBlockBytes = p(CacheBlockBytes)