diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 737b5624..d5a1ddec 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -33,9 +33,6 @@ trait HasCoreplexParameters {
   lazy val cbusConfig = p(CBusConfig)
   lazy val l1tol2Config = p(L1toL2Config)
   lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
-  lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
-  lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
-  lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
   lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
   lazy val nTiles = p(uncore.devices.NTiles)
   lazy val nMemChannels = p(NMemoryChannels)
diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 5237aa8e..15bc225e 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -113,32 +113,6 @@ class BaseCoreplexConfig extends Config (
           dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes)*8)
       }
-      case TLKey("L2toMC") => 
-        TileLinkParameters(
-          coherencePolicy = new MEICoherence(
-            new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = 1,
-          nCachingClients = site(NBanksPerMemoryChannel),
-          nCachelessClients = 0,
-          maxClientXacts = site(NAcquireTransactors) + 2,
-          maxClientsPerPort = site(NBanksPerMemoryChannel),
-          maxManagerXacts = 1,
-          dataBeats = innerDataBeats,
-          dataBits = site(CacheBlockBytes)*8)
-      case TLKey("L2toMMIO") => {
-        TileLinkParameters(
-          coherencePolicy = new MICoherence(
-            new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = 1,
-          nCachingClients = 0,
-          nCachelessClients = 1,
-          maxClientXacts = 4,
-          maxClientsPerPort = 1,
-          maxManagerXacts = 1,
-          dataBeats = innerDataBeats,
-          dataBits = site(CacheBlockBytes) * 8)
-      }
-
       case BootROMFile => "./bootrom/bootrom.img"
       case BufferlessBroadcast => false
       case NTiles => 1
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index 0db7091c..d4c64ffd 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -34,12 +34,6 @@ class BasePlatformConfig extends Config(
           addrBits = site(PAddrBits),
           idBits = site(EdgeIDBits))
         case TLEmitMonitors => true
-        case TLKey("EdgetoSlave") =>
-          site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
-        case TLKey("MCtoEdge") =>
-          site(TLKey("L2toMC")).copy(dataBeats = edgeDataBeats)
-        case TLKey("MMIOtoEdge") =>
-          site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
         case NExtTopInterrupts => 2
         case SOCBusConfig => site(L1toL2Config)
         case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 8c5b7fa2..570a6ea0 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -85,8 +85,6 @@ trait HasPeripheryParameters {
   lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
   lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
   lazy val nMemTLChannels  = if (tMemChannels == BusType.TL)  nMemChannels else 0
-  lazy val edgeSlaveParams = p.alterPartial({ case TLId => "EdgetoSlave" })
-  lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
   lazy val peripheryBusConfig = p(PeripheryBusConfig)
   lazy val socBusConfig = p(SOCBusConfig)
   lazy val cacheBlockBytes = p(CacheBlockBytes)