riscv/rocket-chip
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rocketchip: remove obsolete TL1 config

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This commit is contained in:
Wesley W. Terpstra
2016-11-17 14:24:45 -08:00
parent dfc3a0dafb
commit c82b371354
4 changed files with 0 additions and 37 deletions
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src/main/scala/coreplex/BaseCoreplex.scala
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@ -33,9 +33,6 @@ trait HasCoreplexParameters {
lazy val cbusConfig = p(CBusConfig)
lazy val l1tol2Config = p(L1toL2Config)
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
lazy val nTiles = p(uncore.devices.NTiles)
lazy val nMemChannels = p(NMemoryChannels)