riscv/rocket-chip
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Instantiate PRCI block

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This commit is contained in:
Andrew Waterman 2016-05-02 18:08:33 -07:00
parent 6d1e82bddf
commit c7c8ae5468
4 changed files with 34 additions and 23 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 6f201e73af1c36524367ae74aa1407d1c6863675 Subproject commit 2b96ef2a00cba93ee7a72ac8f7d740dcde70ec52

13
src/main/scala/Configs.scala
View File

@ -25,10 +25,13 @@ class DefaultConfig extends Config (
type PF = PartialFunction[Any,Any] type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
lazy val internalIOAddrMap: AddrMap = { lazy val internalIOAddrMap: AddrMap = {
val debugModule = AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0))) val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
val bootROM = AddrMapEntry("bootrom", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.RX))) entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
val rtc = AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW))) entries += AddrMapEntry("bootrom", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.RX)))
new AddrMap(Seq(debugModule, bootROM, rtc)) entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
for (i <- 0 until site(NTiles))
entries += AddrMapEntry(s"prci$i", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
new AddrMap(entries)
} }
lazy val (globalAddrMap, globalAddrHashMap) = { lazy val (globalAddrMap, globalAddrHashMap) = {
val memSize = 1L << 31 val memSize = 1L << 31
@ -70,10 +73,12 @@ class DefaultConfig extends Config (
for (i <- 0 until site(NTiles)) { for (i <- 0 until site(NTiles)) {
val isa = s"rv${site(XLen)}ima${if (site(UseFPU)) "fd" else ""}" val isa = s"rv${site(XLen)}ima${if (site(UseFPU)) "fd" else ""}"
val timecmpAddr = addrMap("io:int:rtc").start + 8*(i+1) val timecmpAddr = addrMap("io:int:rtc").start + 8*(i+1)
val prciAddr = addrMap(s"io:int:prci$i").start
res append s" $i {\n" res append s" $i {\n"
res append " 0 {\n" res append " 0 {\n"
res append s" isa $isa;\n" res append s" isa $isa;\n"
res append s" timecmp 0x${timecmpAddr.toString(16)};\n" res append s" timecmp 0x${timecmpAddr.toString(16)};\n"
res append s" ipi 0x${prciAddr.toString(16)};\n"
res append " };\n" res append " };\n"
res append " };\n" res append " };\n"
} }

40
src/main/scala/RocketChip.scala
View File

@ -126,21 +126,13 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) } val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
// Connect each tile to the HTIF // Connect each tile to the HTIF
uncore.io.htif.zip(tileList).zipWithIndex.foreach { for (((hl, prci), tile) <- uncore.io.htif zip uncore.io.prci zip tileList) {
case ((hl, tile), i) => tile.io.prci <> prci
// TODO remove // TODO remove HTIF
tile.io.host.id := UInt(i) tile.io.host.id := prci.id
tile.io.host.reset := Reg(next=Reg(next=hl.reset)) tile.io.host.reset := prci.reset
tile.io.host.csr.req <> Queue(hl.csr.req) tile.io.host.csr.req <> Queue(hl.csr.req)
hl.csr.resp <> Queue(tile.io.host.csr.resp) hl.csr.resp <> Queue(tile.io.host.csr.resp)
// TODO move this into PRCI
tile.io.prci.interrupts.mtip := uncore.io.timerIRQs(i)
tile.io.prci.interrupts.msip := Bool(false)
tile.io.prci.interrupts.meip := Bool(false)
tile.io.prci.interrupts.seip := Bool(false)
tile.io.prci.id := UInt(i)
tile.io.prci.reset := Reg(next=Reg(next=hl.reset))
} }
// Connect the uncore to the tile memory ports, HostIO and MemIO // Connect the uncore to the tile memory ports, HostIO and MemIO
@ -171,7 +163,7 @@ class Uncore(implicit val p: Parameters) extends Module
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val htif = Vec(nTiles, new HtifIO).flip val htif = Vec(nTiles, new HtifIO).flip
val timerIRQs = Vec(nTiles, Bool()).asOutput val prci = Vec(nTiles, new PRCITileIO).asOutput
val mmio = new NastiIO val mmio = new NastiIO
} }
@ -218,7 +210,21 @@ class Uncore(implicit val p: Parameters) extends Module
val rtcAddr = ioAddrHashMap("int:rtc") val rtcAddr = ioAddrHashMap("int:rtc")
require(rtc.size <= rtcAddr.region.size) require(rtc.size <= rtcAddr.region.size)
rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port) rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
io.timerIRQs := rtc.io.irqs
for (i <- 0 until nTiles) {
val prci = Module(new PRCI)
val prciAddr = ioAddrHashMap(s"int:prci$i")
prci.io.tl <> mmioNetwork.io.out(prciAddr.port)
prci.io.id := UInt(i)
prci.io.interrupts.mtip := rtc.io.irqs(i)
prci.io.interrupts.meip := Bool(false)
prci.io.interrupts.seip := Bool(false)
prci.io.interrupts.debug := Bool(false)
io.prci(i) := prci.io.tile
io.prci(i).reset := Reg(next=Reg(next=htif.io.cpu(i).reset)) // TODO
}
val bootROM = Module(new ROMSlave(TopUtils.makeBootROM())) val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
val bootROMAddr = ioAddrHashMap("int:bootrom") val bootROMAddr = ioAddrHashMap("int:bootrom")

2
uncore

@ -1 +1 @@
Subproject commit 3e456c87d264c69a568d15ca218eb93836e8ca5d Subproject commit c775dc2c3d62240d89a74153c8e543a93e4834a9