From c7c8ae546898b22df1d58c2ee3b40a0de6471aac Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 2 May 2016 18:08:33 -0700
Subject: [PATCH] Instantiate PRCI block

---
 rocket                          |  2 +-
 src/main/scala/Configs.scala    | 13 +++++++----
 src/main/scala/RocketChip.scala | 40 +++++++++++++++++++--------------
 uncore                          |  2 +-
 4 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/rocket b/rocket
index 6f201e73..2b96ef2a 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 6f201e73af1c36524367ae74aa1407d1c6863675
+Subproject commit 2b96ef2a00cba93ee7a72ac8f7d740dcde70ec52
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 6e643e67..76124253 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -25,10 +25,13 @@ class DefaultConfig extends Config (
     type PF = PartialFunction[Any,Any]
     def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
     lazy val internalIOAddrMap: AddrMap = {
-      val debugModule = AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
-      val bootROM = AddrMapEntry("bootrom", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.RX)))
-      val rtc = AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
-      new AddrMap(Seq(debugModule, bootROM, rtc))
+      val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
+      entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
+      entries += AddrMapEntry("bootrom", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.RX)))
+      entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
+      for (i <- 0 until site(NTiles))
+        entries += AddrMapEntry(s"prci$i", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
+      new AddrMap(entries)
     }
     lazy val (globalAddrMap, globalAddrHashMap) = {
       val memSize = 1L << 31
@@ -70,10 +73,12 @@ class DefaultConfig extends Config (
       for (i <- 0 until site(NTiles)) {
         val isa = s"rv${site(XLen)}ima${if (site(UseFPU)) "fd" else ""}"
         val timecmpAddr = addrMap("io:int:rtc").start + 8*(i+1)
+        val prciAddr = addrMap(s"io:int:prci$i").start
         res append s"  $i {\n"
         res append  "    0 {\n"
         res append s"      isa $isa;\n"
         res append s"      timecmp 0x${timecmpAddr.toString(16)};\n"
+        res append s"      ipi 0x${prciAddr.toString(16)};\n"
         res append  "    };\n"
         res append  "  };\n"
       }
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 3873a745..75ef0eb2 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -126,21 +126,13 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
 
   // Connect each tile to the HTIF
-  uncore.io.htif.zip(tileList).zipWithIndex.foreach {
-    case ((hl, tile), i) =>
-      // TODO remove
-      tile.io.host.id := UInt(i)
-      tile.io.host.reset := Reg(next=Reg(next=hl.reset))
-      tile.io.host.csr.req <> Queue(hl.csr.req)
-      hl.csr.resp <> Queue(tile.io.host.csr.resp)
-
-      // TODO move this into PRCI
-      tile.io.prci.interrupts.mtip := uncore.io.timerIRQs(i)
-      tile.io.prci.interrupts.msip := Bool(false)
-      tile.io.prci.interrupts.meip := Bool(false)
-      tile.io.prci.interrupts.seip := Bool(false)
-      tile.io.prci.id := UInt(i)
-      tile.io.prci.reset := Reg(next=Reg(next=hl.reset))
+  for (((hl, prci), tile) <- uncore.io.htif zip uncore.io.prci zip tileList) {
+    tile.io.prci <> prci
+    // TODO remove HTIF
+    tile.io.host.id := prci.id
+    tile.io.host.reset := prci.reset
+    tile.io.host.csr.req <> Queue(hl.csr.req)
+    hl.csr.resp <> Queue(tile.io.host.csr.resp)
   }
 
   // Connect the uncore to the tile memory ports, HostIO and MemIO
@@ -171,7 +163,7 @@ class Uncore(implicit val p: Parameters) extends Module
     val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
     val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
     val htif = Vec(nTiles, new HtifIO).flip
-    val timerIRQs = Vec(nTiles, Bool()).asOutput
+    val prci = Vec(nTiles, new PRCITileIO).asOutput
     val mmio = new NastiIO
   }
 
@@ -218,7 +210,21 @@ class Uncore(implicit val p: Parameters) extends Module
     val rtcAddr = ioAddrHashMap("int:rtc")
     require(rtc.size <= rtcAddr.region.size)
     rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
-    io.timerIRQs := rtc.io.irqs
+
+    for (i <- 0 until nTiles) {
+      val prci = Module(new PRCI)
+      val prciAddr = ioAddrHashMap(s"int:prci$i")
+      prci.io.tl <> mmioNetwork.io.out(prciAddr.port)
+
+      prci.io.id := UInt(i)
+      prci.io.interrupts.mtip := rtc.io.irqs(i)
+      prci.io.interrupts.meip := Bool(false)
+      prci.io.interrupts.seip := Bool(false)
+      prci.io.interrupts.debug := Bool(false)
+
+      io.prci(i) := prci.io.tile
+      io.prci(i).reset := Reg(next=Reg(next=htif.io.cpu(i).reset)) // TODO
+    }
 
     val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
     val bootROMAddr = ioAddrHashMap("int:bootrom")
diff --git a/uncore b/uncore
index 3e456c87..c775dc2c 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 3e456c87d264c69a568d15ca218eb93836e8ca5d
+Subproject commit c775dc2c3d62240d89a74153c8e543a93e4834a9