riscv/rocket-chip
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two bug fixes to fpu

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This commit is contained in:
Huy Vo
2012-03-31 22:23:51 -07:00
parent a09e8d1c55
commit c7c35322c2
3 changed files with 11 additions and 3 deletions
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4
rocket/src/main/scala/dpath.scala
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@ -423,6 +423,10 @@ class rocketDpath extends Component
io.ctrl.fp_sboard_clr := r_dmem_fp_replay
io.ctrl.fp_sboard_clra := r_dmem_resp_waddr
val r_mem_reg_waddr = Reg(){UFix(width = 5)}
r_mem_reg_waddr := mem_reg_waddr
io.ctrl.fp_sboard_wb_waddr := r_mem_reg_waddr
// processor control regfile write
pcr.io.w.addr := wb_reg_raddr1
pcr.io.w.en := io.ctrl.pcr === PCR_T || io.ctrl.pcr === PCR_S || io.ctrl.pcr === PCR_C