diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 2cfdbf26..d32bd231 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -67,6 +67,7 @@ class ioCtrlDpath extends Bundle()
   val sboard_clra = UFix(5, INPUT);
   val fp_sboard_clr  = Bool(INPUT);
   val fp_sboard_clra = UFix(5, INPUT);
+  val fp_sboard_wb_waddr = UFix(5, INPUT);
   val irq_timer = Bool(INPUT);
   val irq_ipi   = Bool(INPUT);
 }
@@ -639,7 +640,8 @@ class rocketCtrl extends Component
 
     fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen || wb_reg_fp_sboard_set
     fp_sboard.io.w(0).data := Bool(true)
-    fp_sboard.io.w(0).addr := io.dpath.wb_waddr
+    //fp_sboard.io.w(0).addr := io.dpath.wb_waddr
+    fp_sboard.io.w(0).addr := io.dpath.fp_sboard_wb_waddr
 
     fp_sboard.io.w(1).en := io.dpath.fp_sboard_clr
     fp_sboard.io.w(1).data := Bool(false)
@@ -698,7 +700,7 @@ class rocketCtrl extends Component
   // replay mem stage PC on a DTLB miss or a long-latency writeback
   val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val
   val dmem_kill_mem = mem_reg_valid && (io.dtlb_miss || io.dmem.resp_nack)
-  val replay_mem  = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay
+  val replay_mem  = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay || mem_reg_fp_val && io.fpu.nack_mem
   val kill_mem    = dmem_kill_mem || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
   val kill_dcache = io.dtlb_miss  || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
 
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 297bde30..420917cb 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -423,6 +423,10 @@ class rocketDpath extends Component
   io.ctrl.fp_sboard_clr  := r_dmem_fp_replay
   io.ctrl.fp_sboard_clra := r_dmem_resp_waddr
 
+  val r_mem_reg_waddr = Reg(){UFix(width = 5)}
+  r_mem_reg_waddr := mem_reg_waddr
+  io.ctrl.fp_sboard_wb_waddr := r_mem_reg_waddr
+
 	// processor control regfile write
   pcr.io.w.addr := wb_reg_raddr1
   pcr.io.w.en   := io.ctrl.pcr === PCR_T || io.ctrl.pcr === PCR_S || io.ctrl.pcr === PCR_C
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 8696f5a2..f1c36303 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -171,6 +171,7 @@ class ioDpathFPU extends Bundle {
 class ioCtrlFPU extends Bundle {
   val valid = Bool(OUTPUT)
   val nack = Bool(INPUT)
+  val nack_mem = Bool(INPUT)
   val illegal_rm = Bool(INPUT)
   val killx = Bool(OUTPUT)
   val killm = Bool(OUTPUT)
@@ -440,7 +441,7 @@ class rocketFPUDFMAPipe(latency: Int) extends Component
   val fma = new hardfloat.mulAddSubRecodedFloat64_1
   fma.io.op := cmd
   fma.io.roundingMode := rm
-  fma.io.a := in1
+  fma.io.a := in1 
   fma.io.b := in2
   fma.io.c := in3
 
@@ -637,6 +638,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
   val fsr_busy = ctrl.rdfsr && fp_inflight || mem_reg_valid && mem_ctrl.wrfsr || wb_reg_valid && wb_ctrl.wrfsr
   val units_busy = mem_reg_valid && mem_ctrl.fma && (io.sfma.valid && mem_ctrl.single || io.dfma.valid && !mem_ctrl.single)
   io.ctrl.nack := fsr_busy || units_busy || write_port_busy
+  io.ctrl.nack_mem := units_busy
   io.ctrl.dec <> fp_decoder.io.sigs
   // we don't currently support round-max-magnitude (rm=4)
   io.ctrl.illegal_rm := ex_rm(2)