riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

further state optimization in CSRfile when not UseVM

Browse Source
This commit is contained in:
Yunsup Lee 2015-10-25 10:23:46 -07:00
parent 0c587704a7
commit c7235fecb5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/csr.scala
View File

@ -293,7 +293,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
io.fatc := insn_sfence_vm io.fatc := insn_sfence_vm
io.evec := Mux(io.exception || csr_xcpt, (reg_mstatus.prv << 6) + MTVEC, io.evec := Mux(io.exception || csr_xcpt, (reg_mstatus.prv << 6) + MTVEC,
Mux(maybe_insn_redirect_trap, reg_stvec.sextTo(vaddrBitsExtended), Mux(maybe_insn_redirect_trap, reg_stvec.sextTo(vaddrBitsExtended),
Mux(reg_mstatus.prv(1), reg_mepc, reg_sepc))) Mux(reg_mstatus.prv(1) || Bool(!p(UseVM)), reg_mepc, reg_sepc)))
io.ptbr := reg_sptbr io.ptbr := reg_sptbr
io.csr_xcpt := csr_xcpt io.csr_xcpt := csr_xcpt
io.eret := insn_ret || insn_redirect_trap io.eret := insn_ret || insn_redirect_trap