riscv/rocket-chip
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Make FPU pipeline depths configurable

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This commit is contained in:
Andrew Waterman
2014-02-28 13:39:35 -08:00
parent 98b830201a
commit c7110c8389
5 changed files with 17 additions and 14 deletions
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3
rocket/src/main/scala/tile.scala
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@ -6,7 +6,8 @@ import Util._
case class RocketConfiguration(tl: TileLinkConfiguration,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None,
fpu: Option[FPUConfig] = None,
rocc: Option[RocketConfiguration => RoCC] = None,
retireWidth: Int = 1,
vm: Boolean = true,
fastLoadWord: Boolean = true,