From c7110c83892cd1527a8a4622130d5e041180d7c8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 28 Feb 2014 13:39:35 -0800 Subject: [PATCH] Make FPU pipeline depths configurable --- rocket/src/main/scala/core.scala | 4 ++-- rocket/src/main/scala/ctrl.scala | 8 ++++---- rocket/src/main/scala/dpath_util.scala | 8 ++++---- rocket/src/main/scala/fpu.scala | 8 +++++--- rocket/src/main/scala/tile.scala | 3 ++- 5 files changed, 17 insertions(+), 14 deletions(-) diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala index 7b89db98..cd8b694c 100644 --- a/rocket/src/main/scala/core.scala +++ b/rocket/src/main/scala/core.scala @@ -21,8 +21,8 @@ class Core(implicit conf: RocketConfiguration) extends Module val ctrl = Module(new Control) val dpath = Module(new Datapath) - val fpu: FPU = if (conf.fpu) { - val fpu = Module(new FPU(2,3)) + val fpu: FPU = if (!conf.fpu.isEmpty) { + val fpu = Module(new FPU(conf.fpu.get)) dpath.io.fpu <> fpu.io.dpath ctrl.io.fpu <> fpu.io.ctrl fpu diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index bab57620..9e004623 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -318,7 +318,7 @@ class Control(implicit conf: RocketConfiguration) extends Module } var decode_table = XDecode.table - if (conf.fpu) decode_table ++= FDecode.table + if (!conf.fpu.isEmpty) decode_table ++= FDecode.table if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table) @@ -404,11 +404,11 @@ class Control(implicit conf: RocketConfiguration) extends Module (x.map(_._1).reduce(_||_), PriorityMux(x)) val fp_csrs = CSRs.fcsr :: CSRs.frm :: CSRs.fflags :: Nil - val legal_csrs = if (conf.fpu) CSRs.all.toSet else CSRs.all.toSet -- fp_csrs + val legal_csrs = if (!conf.fpu.isEmpty) CSRs.all.toSet else CSRs.all.toSet -- fp_csrs val id_csr_addr = io.dpath.inst(31,20) val id_csr_en = id_csr != CSR.N - val id_csr_fp = Bool(conf.fpu) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs) + val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs) val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr) val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr) val id_csr_privileged = id_csr_en && @@ -604,7 +604,7 @@ class Control(implicit conf: RocketConfiguration) extends Module sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr) sboard.clear(io.dpath.ll_wen, io.dpath.ll_waddr) - val id_stall_fpu = if (conf.fpu) { + val id_stall_fpu = if (!conf.fpu.isEmpty) { val fp_sboard = new Scoreboard(32) fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr) fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra) diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 3d1922b1..a0082388 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -214,9 +214,9 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS val read_mapping = collection.mutable.Map[Int,Bits]( - CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)), - CSRs.frm -> (if (conf.fpu) reg_frm else UInt(0)), - CSRs.fcsr -> (if (conf.fpu) Cat(reg_frm, reg_fflags) else UInt(0)), + CSRs.fflags -> (if (!conf.fpu.isEmpty) reg_fflags else UInt(0)), + CSRs.frm -> (if (!conf.fpu.isEmpty) reg_frm else UInt(0)), + CSRs.fcsr -> (if (!conf.fpu.isEmpty) Cat(reg_frm, reg_fflags) else UInt(0)), CSRs.cycle -> reg_time, CSRs.time -> reg_time, CSRs.instret -> reg_instret, @@ -258,7 +258,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module reg_status.zero := 0 if (!conf.vm) reg_status.vm := false if (conf.rocc.isEmpty) reg_status.er := false - if (!conf.fpu) reg_status.ef := false + if (conf.fpu.isEmpty) reg_status.ef := false } when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { reg_frm := wdata } diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index 15c3f83f..a9277aca 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -6,6 +6,8 @@ import Util._ import FPConstants._ import uncore.constants.MemoryOpConstants._ +case class FPUConfig(sfmaLatency: Int = 2, dfmaLatency: Int = 3) + object FPConstants { val FCMD_ADD = Bits("b000000") @@ -432,7 +434,7 @@ class FPUDFMAPipe(val latency: Int) extends Module io.exc := Pipe(valid, fma.io.exceptionFlags, latency-1).bits } -class FPU(sfma_latency: Int, dfma_latency: Int) extends Module +class FPU(conf: FPUConfig) extends Module { val io = new Bundle { val ctrl = (new CtrlFPUIO).flip @@ -501,7 +503,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val cmd_fma = mem_ctrl.cmd === FCMD_MADD || mem_ctrl.cmd === FCMD_MSUB || mem_ctrl.cmd === FCMD_NMADD || mem_ctrl.cmd === FCMD_NMSUB val cmd_addsub = mem_ctrl.cmd === FCMD_ADD || mem_ctrl.cmd === FCMD_SUB - val sfma = Module(new FPUSFMAPipe(sfma_latency)) + val sfma = Module(new FPUSFMAPipe(conf.sfmaLatency)) sfma.io.valid := io.sfma.valid || ex_reg_valid && ctrl.fma && ctrl.single sfma.io.in1 := Mux(io.sfma.valid, io.sfma.in1, ex_rs1) sfma.io.in2 := Mux(io.sfma.valid, io.sfma.in2, ex_rs2) @@ -511,7 +513,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module io.sfma.out := sfma.io.out io.sfma.exc := sfma.io.exc - val dfma = Module(new FPUDFMAPipe(dfma_latency)) + val dfma = Module(new FPUDFMAPipe(conf.dfmaLatency)) dfma.io.valid := io.dfma.valid || ex_reg_valid && ctrl.fma && !ctrl.single dfma.io.in1 := Mux(io.dfma.valid, io.dfma.in1, ex_rs1) dfma.io.in2 := Mux(io.dfma.valid, io.dfma.in2, ex_rs2) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 99173748..e2e0a60f 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -6,7 +6,8 @@ import Util._ case class RocketConfiguration(tl: TileLinkConfiguration, icache: ICacheConfig, dcache: DCacheConfig, - fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None, + fpu: Option[FPUConfig] = None, + rocc: Option[RocketConfiguration => RoCC] = None, retireWidth: Int = 1, vm: Boolean = true, fastLoadWord: Boolean = true,