Make FPU pipeline depths configurable
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@ -318,7 +318,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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}
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var decode_table = XDecode.table
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if (conf.fpu) decode_table ++= FDecode.table
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if (!conf.fpu.isEmpty) decode_table ++= FDecode.table
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if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table
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val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
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@ -404,11 +404,11 @@ class Control(implicit conf: RocketConfiguration) extends Module
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(x.map(_._1).reduce(_||_), PriorityMux(x))
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val fp_csrs = CSRs.fcsr :: CSRs.frm :: CSRs.fflags :: Nil
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val legal_csrs = if (conf.fpu) CSRs.all.toSet else CSRs.all.toSet -- fp_csrs
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val legal_csrs = if (!conf.fpu.isEmpty) CSRs.all.toSet else CSRs.all.toSet -- fp_csrs
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val id_csr_addr = io.dpath.inst(31,20)
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val id_csr_en = id_csr != CSR.N
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val id_csr_fp = Bool(conf.fpu) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
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val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
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val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
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val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr)
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val id_csr_privileged = id_csr_en &&
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@ -604,7 +604,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr)
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sboard.clear(io.dpath.ll_wen, io.dpath.ll_waddr)
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val id_stall_fpu = if (conf.fpu) {
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val id_stall_fpu = if (!conf.fpu.isEmpty) {
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val fp_sboard = new Scoreboard(32)
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fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr)
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fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)
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