riscv/rocket-chip
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Make FPU pipeline depths configurable

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This commit is contained in:
Andrew Waterman
2014-02-28 13:39:35 -08:00
parent 98b830201a
commit c7110c8389
5 changed files with 17 additions and 14 deletions
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4
rocket/src/main/scala/core.scala
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@ -21,8 +21,8 @@ class Core(implicit conf: RocketConfiguration) extends Module
val ctrl = Module(new Control)
val dpath = Module(new Datapath)
val fpu: FPU = if (conf.fpu) {
val fpu = Module(new FPU(2,3))
val fpu: FPU = if (!conf.fpu.isEmpty) {
val fpu = Module(new FPU(conf.fpu.get))
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
fpu