IntNodes: moved from tilelink to their own package

src/main/scala/coreplex/BaseCoreplex.scala

@@ -5,6 +5,7 @@ package freechips.rocketchip.coreplex
 import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.interrupts._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.tile.{BaseTile, TileParams, SharedMemoryTLEdge, HasExternallyDrivenTileConstants}

src/main/scala/coreplex/InterruptBus.scala

@@ -5,7 +5,7 @@ package freechips.rocketchip.coreplex
 import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
 
 /** Collects interrupts from internal and external devices and feeds them into the PLIC */ 
 class InterruptBusWrapper(implicit p: Parameters) {

src/main/scala/coreplex/RocketCoreplex.scala

@@ -9,6 +9,7 @@ import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugM
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 
 case class TLNodeChain(in: TLInwardNode, out: TLOutwardNode)

src/main/scala/coreplex/package.scala

@@ -2,7 +2,8 @@
 
 package freechips.rocketchip
 
-import freechips.rocketchip.tilelink._
+import freechips.rocketchip.tilelink.TLOutwardNode
+import freechips.rocketchip.interrupts.IntOutwardNode
 
 package object coreplex
 {