diff --git a/src/main/scala/amba/ahb/RegisterRouter.scala b/src/main/scala/amba/ahb/RegisterRouter.scala index da1960d7..59a81611 100644 --- a/src/main/scala/amba/ahb/RegisterRouter.scala +++ b/src/main/scala/amba/ahb/RegisterRouter.scala @@ -6,7 +6,7 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} +import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.{HeterogeneousBag, MaskGen} import scala.math.{min,max} diff --git a/src/main/scala/amba/apb/RegisterRouter.scala b/src/main/scala/amba/apb/RegisterRouter.scala index f83c38c9..2ebb57d8 100644 --- a/src/main/scala/amba/apb/RegisterRouter.scala +++ b/src/main/scala/amba/apb/RegisterRouter.scala @@ -6,7 +6,7 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} +import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.HeterogeneousBag import scala.math.{min,max} diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala index 32d0b1de..0da5da31 100644 --- a/src/main/scala/amba/axi4/RegisterRouter.scala +++ b/src/main/scala/amba/axi4/RegisterRouter.scala @@ -6,7 +6,7 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} +import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.{HeterogeneousBag, MaskGen} import scala.math.{min,max} diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index bb004313..121ef9d1 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -5,6 +5,7 @@ package freechips.rocketchip.coreplex import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.tile.{BaseTile, TileParams, SharedMemoryTLEdge, HasExternallyDrivenTileConstants} diff --git a/src/main/scala/coreplex/InterruptBus.scala b/src/main/scala/coreplex/InterruptBus.scala index 4c04d992..3e639f79 100644 --- a/src/main/scala/coreplex/InterruptBus.scala +++ b/src/main/scala/coreplex/InterruptBus.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.coreplex import Chisel._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ /** Collects interrupts from internal and external devices and feeds them into the PLIC */ class InterruptBusWrapper(implicit p: Parameters) { diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 442b655d..650a5098 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugM import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ case class TLNodeChain(in: TLInwardNode, out: TLOutwardNode) diff --git a/src/main/scala/coreplex/package.scala b/src/main/scala/coreplex/package.scala index a93eef0c..fbd07861 100644 --- a/src/main/scala/coreplex/package.scala +++ b/src/main/scala/coreplex/package.scala @@ -2,7 +2,8 @@ package freechips.rocketchip -import freechips.rocketchip.tilelink._ +import freechips.rocketchip.tilelink.TLOutwardNode +import freechips.rocketchip.interrupts.IntOutwardNode package object coreplex { diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 37f85ff2..f2d2a56f 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.regmapper._ import freechips.rocketchip.rocket.Instructions import freechips.rocketchip.tile.XLen import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ /** Constant values used by both Debug Bus Response & Request diff --git a/src/main/scala/devices/tilelink/Clint.scala b/src/main/scala/devices/tilelink/Clint.scala index 0f80640b..9cc83030 100644 --- a/src/main/scala/devices/tilelink/Clint.scala +++ b/src/main/scala/devices/tilelink/Clint.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tile.XLen import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import scala.math.{min,max} diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index 73c9d681..a6ede5b7 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -10,6 +10,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tile.XLen import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import scala.math.min diff --git a/src/main/scala/interrupts/Bundles.scala b/src/main/scala/interrupts/Bundles.scala new file mode 100644 index 00000000..86691f9e --- /dev/null +++ b/src/main/scala/interrupts/Bundles.scala @@ -0,0 +1,12 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.interrupts + +import Chisel._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util._ + +class SyncInterrupts(params: IntEdge) extends GenericParameterizedBundle(params) +{ + val sync = Vec(params.source.num, Bool()) +} diff --git a/src/main/scala/interrupts/Crossing.scala b/src/main/scala/interrupts/Crossing.scala new file mode 100644 index 00000000..67ba2075 --- /dev/null +++ b/src/main/scala/interrupts/Crossing.scala @@ -0,0 +1,20 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.interrupts + +import Chisel._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.util.SynchronizerShiftReg +import freechips.rocketchip.diplomacy._ + +@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") +class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule +{ + val intnode = IntAdapterNode() + + lazy val module = new LazyModuleImp(this) { + (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => + out := SynchronizerShiftReg(in, sync) + } + } +} diff --git a/src/main/scala/interrupts/Nodes.scala b/src/main/scala/interrupts/Nodes.scala new file mode 100644 index 00000000..5f5f86b8 --- /dev/null +++ b/src/main/scala/interrupts/Nodes.scala @@ -0,0 +1,62 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.interrupts + +import Chisel._ +import chisel3.internal.sourceinfo.SourceInfo +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ + +object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, Vec[Bool]] +{ + def edge(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo) = IntEdge(pd, pu, p, sourceInfo) + def bundle(e: IntEdge) = Vec(e.source.num, Bool()) + def render(e: IntEdge) = RenderedEdge(colour = "#0000ff" /* blue */, label = e.source.sources.map(_.range.size).sum.toString, flipped = true) + + override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSourcePortParameters = + pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) }) + override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSinkPortParameters = + pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) }) +} + +case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams) +case class IntSinkNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends SinkNode(IntImp)(portParams) +case class IntAdapterNode( + sourceFn: IntSourcePortParameters => IntSourcePortParameters = { s => s }, + sinkFn: IntSinkPortParameters => IntSinkPortParameters = { s => s }, + num: Range.Inclusive = 0 to 999)( + implicit valName: ValName) + extends AdapterNode(IntImp)(sourceFn, sinkFn, num) +case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp)() + +case class IntNexusNode( + sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters, + sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters, + numSourcePorts: Range.Inclusive = 0 to 128, + numSinkPorts: Range.Inclusive = 0 to 128)( + implicit valName: ValName) + extends NexusNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts) + +object IntSyncImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, SyncInterrupts] +{ + def edge(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo) = IntEdge(pd, pu, p, sourceInfo) + def bundle(e: IntEdge) = new SyncInterrupts(e) + def render(e: IntEdge) = RenderedEdge(colour = "#ff00ff" /* purple */, label = e.source.sources.map(_.range.size).sum.toString, flipped = true) + + override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]): IntSourcePortParameters = + pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) }) + override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]): IntSinkPortParameters = + pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) }) +} + +case class IntSyncIdentityNode()(implicit valName: ValName) extends IdentityNode(IntSyncImp)() + +case class IntSyncSourceNode()(implicit valName: ValName) + extends MixedAdapterNode(IntImp, IntSyncImp)( + dFn = { p => p }, + uFn = { p => p }) + +case class IntSyncSinkNode()(implicit valName: ValName) + extends MixedAdapterNode(IntSyncImp, IntImp)( + dFn = { p => p }, + uFn = { p => p }) diff --git a/src/main/scala/interrupts/Parameters.scala b/src/main/scala/interrupts/Parameters.scala new file mode 100644 index 00000000..bb3e37a1 --- /dev/null +++ b/src/main/scala/interrupts/Parameters.scala @@ -0,0 +1,61 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.interrupts + +import Chisel._ +import chisel3.internal.sourceinfo.SourceInfo +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ + +// A potentially empty half-open range; [start, end) +case class IntRange(start: Int, end: Int) +{ + require (start >= 0) + require (start <= end) + def size = end - start + def overlaps(x: IntRange) = start < x.end && x.start < end + def offset(x: Int) = IntRange(x+start, x+end) +} + +object IntRange +{ + implicit def apply(end: Int): IntRange = apply(0, end) +} + +case class IntSourceParameters( + range: IntRange, + resources: Seq[Resource] = Seq(), + nodePath: Seq[BaseNode] = Seq()) +{ + val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") +} + +case class IntSinkParameters( + nodePath: Seq[BaseNode] = Seq()) +{ + val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") +} + +case class IntSourcePortParameters(sources: Seq[IntSourceParameters]) +{ + val num = sources.map(_.range.size).sum + // The interrupts mapping must not overlap + sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) } + // The interrupts must perfectly cover the range + require (sources.isEmpty || sources.map(_.range.end).max == num) +} +object IntSourcePortSimple +{ + def apply(num: Int = 1, ports: Int = 1, sources: Int = 1, resources: Seq[Resource] = Nil) = + if (num == 0) Nil else + Seq.fill(ports)(IntSourcePortParameters(Seq.fill(sources)(IntSourceParameters(range = IntRange(0, num), resources = resources)))) +} + +case class IntSinkPortParameters(sinks: Seq[IntSinkParameters]) +object IntSinkPortSimple +{ + def apply(ports: Int = 1, sinks: Int = 1) = + Seq.fill(ports)(IntSinkPortParameters(Seq.fill(sinks)(IntSinkParameters()))) +} + +case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters, params: Parameters, sourceInfo: SourceInfo) diff --git a/src/main/scala/interrupts/Xbar.scala b/src/main/scala/interrupts/Xbar.scala new file mode 100644 index 00000000..556974ef --- /dev/null +++ b/src/main/scala/interrupts/Xbar.scala @@ -0,0 +1,23 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.interrupts + +import Chisel._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ + +class IntXbar()(implicit p: Parameters) extends LazyModule +{ + val intnode = IntNexusNode( + sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, + sourceFn = { seq => + IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { + case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) + }.flatten) + }) + + lazy val module = new LazyModuleImp(this) { + val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten + intnode.out.foreach { case (o, _) => o := cat } + } +} diff --git a/src/main/scala/interrupts/package.scala b/src/main/scala/interrupts/package.scala new file mode 100644 index 00000000..9b2bef75 --- /dev/null +++ b/src/main/scala/interrupts/package.scala @@ -0,0 +1,14 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip + +import Chisel._ +import freechips.rocketchip.diplomacy._ + +package object interrupts +{ + type IntInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] + type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] + type IntSyncInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts] + type IntSyncOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts] +} diff --git a/src/main/scala/rocket/BusErrorUnit.scala b/src/main/scala/rocket/BusErrorUnit.scala index 7ba2bc2d..d3928fee 100644 --- a/src/main/scala/rocket/BusErrorUnit.scala +++ b/src/main/scala/rocket/BusErrorUnit.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ trait BusErrors extends Bundle { def toErrorList: List[Option[Valid[UInt]]] diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index dd8d002b..b154dfbc 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -10,6 +10,7 @@ import freechips.rocketchip.coreplex.CacheBlockBytes import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala index dcccada3..0043089d 100644 --- a/src/main/scala/tile/Interrupts.scala +++ b/src/main/scala/tile/Interrupts.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.tile import Chisel._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.tilelink.{IntSinkNode, IntSinkPortSimple} +import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} import freechips.rocketchip.util._ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 98849fef..3fe5fe51 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.coreplex._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ case class RocketTileParams( diff --git a/src/main/scala/tilelink/IntNodes.scala b/src/main/scala/tilelink/IntNodes.scala deleted file mode 100644 index 2cc6aa61..00000000 --- a/src/main/scala/tilelink/IntNodes.scala +++ /dev/null @@ -1,121 +0,0 @@ -// See LICENSE.SiFive for license details. - -package freechips.rocketchip.tilelink - -import Chisel._ -import chisel3.internal.sourceinfo.SourceInfo -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util.SynchronizerShiftReg -import scala.collection.mutable.ListBuffer -import scala.math.max - -// A potentially empty half-open range; [start, end) -case class IntRange(start: Int, end: Int) -{ - require (start >= 0) - require (start <= end) - def size = end - start - def overlaps(x: IntRange) = start < x.end && x.start < end - def offset(x: Int) = IntRange(x+start, x+end) -} - -object IntRange -{ - implicit def apply(end: Int): IntRange = apply(0, end) -} - -case class IntSourceParameters( - range: IntRange, - resources: Seq[Resource] = Seq(), - nodePath: Seq[BaseNode] = Seq()) -{ - val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") -} - -case class IntSinkParameters( - nodePath: Seq[BaseNode] = Seq()) -{ - val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") -} - -case class IntSourcePortParameters(sources: Seq[IntSourceParameters]) -{ - val num = sources.map(_.range.size).sum - // The interrupts mapping must not overlap - sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) } - // The interrupts must perfectly cover the range - require (sources.isEmpty || sources.map(_.range.end).max == num) -} -object IntSourcePortSimple -{ - def apply(num: Int = 1, ports: Int = 1, sources: Int = 1, resources: Seq[Resource] = Nil) = - if (num == 0) Nil else - Seq.fill(ports)(IntSourcePortParameters(Seq.fill(sources)(IntSourceParameters(range = IntRange(0, num), resources = resources)))) -} - -case class IntSinkPortParameters(sinks: Seq[IntSinkParameters]) -object IntSinkPortSimple -{ - def apply(ports: Int = 1, sinks: Int = 1) = - Seq.fill(ports)(IntSinkPortParameters(Seq.fill(sinks)(IntSinkParameters()))) -} - -case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters, params: Parameters, sourceInfo: SourceInfo) - -object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, Vec[Bool]] -{ - def edge(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo) = IntEdge(pd, pu, p, sourceInfo) - def bundle(e: IntEdge) = Vec(e.source.num, Bool()) - def render(e: IntEdge) = RenderedEdge(colour = "#0000ff" /* blue */, label = e.source.sources.map(_.range.size).sum.toString, flipped = true) - - override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSourcePortParameters = - pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) }) - override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSinkPortParameters = - pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) }) -} - -case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams) -case class IntSinkNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends SinkNode(IntImp)(portParams) -case class IntAdapterNode( - sourceFn: IntSourcePortParameters => IntSourcePortParameters = { s => s }, - sinkFn: IntSinkPortParameters => IntSinkPortParameters = { s => s }, - num: Range.Inclusive = 0 to 999)( - implicit valName: ValName) - extends AdapterNode(IntImp)(sourceFn, sinkFn, num) -case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp)() - -case class IntNexusNode( - sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters, - sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters, - numSourcePorts: Range.Inclusive = 0 to 128, - numSinkPorts: Range.Inclusive = 0 to 128)( - implicit valName: ValName) - extends NexusNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts) - -class IntXbar()(implicit p: Parameters) extends LazyModule -{ - val intnode = IntNexusNode( - sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, - sourceFn = { seq => - IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { - case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) - }.flatten) - }) - - lazy val module = new LazyModuleImp(this) { - val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten - intnode.out.foreach { case (o, _) => o := cat } - } -} - -class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule -{ - val intnode = IntAdapterNode() - - lazy val module = new LazyModuleImp(this) { - (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => - out := SynchronizerShiftReg(in, sync) - } - } -} diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala index dc49e797..44df9669 100644 --- a/src/main/scala/tilelink/RegisterRouter.scala +++ b/src/main/scala/tilelink/RegisterRouter.scala @@ -6,6 +6,7 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ +import freechips.rocketchip.interrupts._ import freechips.rocketchip.util.HeterogeneousBag import scala.math.{min,max} diff --git a/src/main/scala/tilelink/package.scala b/src/main/scala/tilelink/package.scala index e0a165b7..96e8edfa 100644 --- a/src/main/scala/tilelink/package.scala +++ b/src/main/scala/tilelink/package.scala @@ -15,7 +15,4 @@ package object tilelink type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle] type TLMixedNode = MixedNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle, TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle] - - type IntInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] - type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] }