riscv/rocket-chip
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Remove Option from success flag in coreplex; just use a sane default.

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This commit is contained in:
Henry Cook 2016-09-15 12:19:22 -07:00
parent 9e2b0aad65
commit c6f252a913
3 changed files with 9 additions and 8 deletions
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9
src/main/scala/coreplex/Coreplex.scala
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@ -57,14 +57,16 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
val interrupts = Vec(c.nExtInterrupts, Bool()).asInput val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
val debug = new DebugBusIO()(p).flip val debug = new DebugBusIO()(p).flip
val prci = Vec(c.nTiles, new PRCITileIO).flip val prci = Vec(c.nTiles, new PRCITileIO).flip
val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT)) val success = Bool(OUTPUT)
} }
def hasSuccessFlag: Boolean = false
val io = new CoreplexIO val io = new CoreplexIO
} }
class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) { class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
// Coreplex doesn't know when to stop running
io.success := Bool(false)
// Build a set of Tiles // Build a set of Tiles
val tileResets = Wire(Vec(tc.nTiles, Bool())) val tileResets = Wire(Vec(tc.nTiles, Bool()))
val tileList = p(BuildTiles).zip(tileResets).map { val tileList = p(BuildTiles).zip(tileResets).map {
@ -164,6 +166,5 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
} }
class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) { class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
override def hasSuccessFlag = true io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
} }

4
src/main/scala/rocketchip/TestHarness.scala
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@ -136,12 +136,12 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
} }
def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO, def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO,
dutsuccess: Option[Bool], tbsuccess: Bool) = { dutsuccess: Bool, tbsuccess: Bool) = {
io.clk := tbclk io.clk := tbclk
io.reset := tbreset io.reset := tbreset
dutio <> io.debug dutio <> io.debug
tbsuccess := dutsuccess.getOrElse(io.exit === 1) tbsuccess := dutsuccess || io.exit === 1
when (io.exit >= 2) { when (io.exit >= 2) {
printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1) printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1)
stop(1) stop(1)

4
src/main/scala/rocketchip/Top.scala
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@ -29,7 +29,7 @@ abstract class BaseTop(val p: Parameters) extends LazyModule {
} }
class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) { class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
val success = c.hasSuccessFlag.option(Bool(OUTPUT)) val success = Bool(OUTPUT)
} }
class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) { class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
@ -65,7 +65,7 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
val coreplex = p(BuildCoreplex)(p, c) val coreplex = p(BuildCoreplex)(p, c)
val io: B = b(coreplex) val io: B = b(coreplex)
io.success zip coreplex.io.success map { case (x, y) => x := y } io.success := coreplex.io.success
val mmioNetwork = c.hasExtMMIOPort.option( val mmioNetwork = c.hasExtMMIOPort.option(
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))( Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(