From c6f252a9136eb789f16a0daae18bdf266268fef9 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 12:19:22 -0700
Subject: [PATCH] Remove Option from success flag in coreplex; just use a sane
 default.

---
 src/main/scala/coreplex/Coreplex.scala      | 9 +++++----
 src/main/scala/rocketchip/TestHarness.scala | 4 ++--
 src/main/scala/rocketchip/Top.scala         | 4 ++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala
index 2da93f9f..619f6410 100644
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@@ -57,14 +57,16 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
     val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
     val debug = new DebugBusIO()(p).flip
     val prci = Vec(c.nTiles, new PRCITileIO).flip
-    val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
+    val success = Bool(OUTPUT)
   }
 
-  def hasSuccessFlag: Boolean = false
   val io = new CoreplexIO
 }
 
 class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
+  // Coreplex doesn't know when to stop running
+  io.success := Bool(false)
+
   // Build a set of Tiles
   val tileResets = Wire(Vec(tc.nTiles, Bool()))
   val tileList = p(BuildTiles).zip(tileResets).map {
@@ -164,6 +166,5 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
 }
 
 class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
-  override def hasSuccessFlag = true
-  io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
+  io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
 }
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 9e073499..7b7dd239 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -136,12 +136,12 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
   }
 
   def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO,
-      dutsuccess: Option[Bool], tbsuccess: Bool) = {
+      dutsuccess: Bool, tbsuccess: Bool) = {
     io.clk := tbclk
     io.reset := tbreset
     dutio <> io.debug
 
-    tbsuccess := dutsuccess.getOrElse(io.exit === 1)
+    tbsuccess := dutsuccess || io.exit === 1
     when (io.exit >= 2) {
       printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1)
       stop(1)
diff --git a/src/main/scala/rocketchip/Top.scala b/src/main/scala/rocketchip/Top.scala
index c56ffc46..46610458 100644
--- a/src/main/scala/rocketchip/Top.scala
+++ b/src/main/scala/rocketchip/Top.scala
@@ -29,7 +29,7 @@ abstract class BaseTop(val p: Parameters) extends LazyModule {
 }
 
 class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
-  val success = c.hasSuccessFlag.option(Bool(OUTPUT))
+  val success = Bool(OUTPUT)
 }
 
 class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
@@ -65,7 +65,7 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   val coreplex = p(BuildCoreplex)(p, c)
   val io: B = b(coreplex)
 
-  io.success zip coreplex.io.success map { case (x, y) => x := y }
+  io.success := coreplex.io.success
 
   val mmioNetwork = c.hasExtMMIOPort.option(
     Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(