riscv/rocket-chip
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Remove Option from success flag in coreplex; just use a sane default.

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This commit is contained in:
Henry Cook
2016-09-15 12:19:22 -07:00
parent 9e2b0aad65
commit c6f252a913
3 changed files with 9 additions and 8 deletions
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4
src/main/scala/rocketchip/TestHarness.scala
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@ -136,12 +136,12 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
}
def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO,
dutsuccess: Option[Bool], tbsuccess: Bool) = {
dutsuccess: Bool, tbsuccess: Bool) = {
io.clk := tbclk
io.reset := tbreset
dutio <> io.debug
tbsuccess := dutsuccess.getOrElse(io.exit === 1)
tbsuccess := dutsuccess || io.exit === 1
when (io.exit >= 2) {
printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1)
stop(1)

4
src/main/scala/rocketchip/Top.scala
View File

@ -29,7 +29,7 @@ abstract class BaseTop(val p: Parameters) extends LazyModule {
}
class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
val success = c.hasSuccessFlag.option(Bool(OUTPUT))
val success = Bool(OUTPUT)
}
class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
@ -65,7 +65,7 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
val coreplex = p(BuildCoreplex)(p, c)
val io: B = b(coreplex)
io.success zip coreplex.io.success map { case (x, y) => x := y }
io.success := coreplex.io.success
val mmioNetwork = c.hasExtMMIOPort.option(
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(