Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always right-justified. However, for narrow writes, the data must actually be aligned within the byte lanes. This commit changes some of the converters in order to fix this issue. There was a bug in the L2 cache in which a merged get request was causing the tracker to read the old data from the data array, overwriting the updated data acquired from outer memory. Changed it so that pending_reads is no longer set if the data in the buffer is already valid. There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and FinishToDst types used client_id for routing to managers. This caused bits to get cut off, which meant the Finish messages could not be routed correctly. Changed to use manager_id instead.
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@ -142,7 +142,7 @@ class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
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class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new WithTraceGen ++ new GroundTestConfig)
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class FancyMemtestConfig extends Config(
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new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
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new With2Cores ++ new With2MemoryChannels ++ new With4BanksPerMemChannel ++
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new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
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class MemoryMuxMemtestConfig extends Config(
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