From c5838dd9b3e5863f0fd0aed87f7f7df8bf74d902 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 1 Apr 2016 17:53:59 -0700 Subject: [PATCH] Fix narrow read/write behavior for AXI converters and fix L2 bugs Until recently, we were assuming that the data channel in AXI was always right-justified. However, for narrow writes, the data must actually be aligned within the byte lanes. This commit changes some of the converters in order to fix this issue. There was a bug in the L2 cache in which a merged get request was causing the tracker to read the old data from the data array, overwriting the updated data acquired from outer memory. Changed it so that pending_reads is no longer set if the data in the buffer is already valid. There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and FinishToDst types used client_id for routing to managers. This caused bits to get cut off, which meant the Finish messages could not be routed correctly. Changed to use manager_id instead. --- .travis.yml | 1 + chisel3 | 2 +- csrc/mm.cc | 18 ++++++++++-------- csrc/mm.h | 5 +---- csrc/mm_dramsim2.cc | 7 ++++--- csrc/mm_dramsim2.h | 5 +---- firrtl | 2 +- groundtest | 2 +- junctions | 2 +- rocket | 2 +- src/main/scala/TestBench.scala | 6 +++--- src/main/scala/TestConfigs.scala | 2 +- uncore | 2 +- 13 files changed, 27 insertions(+), 29 deletions(-) diff --git a/.travis.yml b/.travis.yml index 8cd92833..25f1ad63 100644 --- a/.travis.yml +++ b/.travis.yml @@ -50,6 +50,7 @@ env: - CONFIG=MemoryMuxMemtestConfig - CONFIG=BroadcastRegressionTestConfig - CONFIG=CacheRegressionTestConfig + - CONFIG=NastiConverterTestConfig - CONFIG=UnitTestConfig - CONFIG=SplitL2MetadataTestConfig diff --git a/chisel3 b/chisel3 index 9b114817..f9689cab 160000 --- a/chisel3 +++ b/chisel3 @@ -1 +1 @@ -Subproject commit 9b114817b00d793e8e58e9c8bd6beefd31d458ea +Subproject commit f9689cab3bbb5cb2cddbb429bc30d630c886034d diff --git a/csrc/mm.cc b/csrc/mm.cc index c1344046..caad38dd 100644 --- a/csrc/mm.cc +++ b/csrc/mm.cc @@ -9,20 +9,22 @@ void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size) { + strb &= ((1 << size) - 1) << (addr % word_size); + if (addr > this->size) { fprintf(stderr, "Invalid write address %lx\n", addr); exit(EXIT_FAILURE); } - uint8_t *base = this->data + addr; - for (int i = 0; i < size; i++) { + uint8_t *base = this->data + (addr / word_size) * word_size; + for (int i = 0; i < word_size; i++) { if (strb & 1) base[i] = data[i]; strb >>= 1; } } -std::vector mm_t::read(uint64_t addr, uint64_t size) +std::vector mm_t::read(uint64_t addr) { if (addr > this->size) { fprintf(stderr, "Invalid read address %lx\n", addr); @@ -30,7 +32,7 @@ std::vector mm_t::read(uint64_t addr, uint64_t size) } uint8_t *base = this->data + addr; - return std::vector(base, base + size); + return std::vector(base, base + word_size); } void mm_t::init(size_t sz, int wsz, int lsz) @@ -81,19 +83,19 @@ void mm_magic_t::tick( bool b_fire = b_valid() && b_ready; if (ar_fire) { - uint64_t word_size = (1 << ar_size); + uint64_t start_addr = (ar_addr / word_size) * word_size; for (int i = 0; i <= ar_len; i++) { - auto dat = read(ar_addr + i * word_size, word_size); + auto dat = read(start_addr + i * word_size); rresp.push(mm_rresp_t(ar_id, dat, i == ar_len)); } } if (aw_fire) { store_addr = aw_addr; - store_size = (1 << aw_size); store_id = aw_id; - store_inflight = true; store_count = aw_len + 1; + store_size = 1 << aw_size; + store_inflight = true; } if (w_fire) { diff --git a/csrc/mm.h b/csrc/mm.h index c57ebd4d..178b76c4 100644 --- a/csrc/mm.h +++ b/csrc/mm.h @@ -7,9 +7,6 @@ #include #include -void write_masked_data( - uint8_t *base, uint8_t *data, uint64_t strb, uint64_t size); - class mm_t { public: @@ -58,7 +55,7 @@ class mm_t virtual size_t get_line_size() { return line_size; } void write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size); - std::vector read(uint64_t addr, uint64_t size); + std::vector read(uint64_t addr); virtual ~mm_t(); diff --git a/csrc/mm_dramsim2.cc b/csrc/mm_dramsim2.cc index 68cf4973..81ef48ab 100644 --- a/csrc/mm_dramsim2.cc +++ b/csrc/mm_dramsim2.cc @@ -18,8 +18,9 @@ using namespace DRAMSim; void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle) { auto req = rreq[address].front(); + uint64_t start_addr = (address / word_size) * word_size; for (int i = 0; i < req.len; i++) { - auto dat = read(address + i * req.size, req.size); + auto dat = read(start_addr + i * word_size); rresp.push(mm_rresp_t(req.id, dat, (i == req.len - 1))); } rreq[address].pop(); @@ -84,15 +85,15 @@ void mm_dramsim2_t::tick( bool b_fire = b_valid() && b_ready; if (ar_fire) { - rreq[ar_addr].push(mm_req_t(ar_id, 1 << ar_size, ar_len + 1, ar_addr)); + rreq[ar_addr].push(mm_req_t(ar_id, ar_len + 1, ar_addr)); mem->addTransaction(false, ar_addr); } if (aw_fire) { store_addr = aw_addr; - store_size = (1 << aw_size); store_id = aw_id; store_count = aw_len + 1; + store_size = 1 << aw_size; store_inflight = true; } diff --git a/csrc/mm_dramsim2.h b/csrc/mm_dramsim2.h index eb6175b4..9c4e748a 100644 --- a/csrc/mm_dramsim2.h +++ b/csrc/mm_dramsim2.h @@ -11,14 +11,12 @@ struct mm_req_t { uint64_t id; - uint64_t size; uint64_t len; uint64_t addr; - mm_req_t(uint64_t id, uint64_t size, uint64_t len, uint64_t addr) + mm_req_t(uint64_t id, uint64_t len, uint64_t addr) { this->id = id; - this->size = size; this->len = len; this->addr = addr; } @@ -26,7 +24,6 @@ struct mm_req_t { mm_req_t() { this->id = 0; - this->size = 0; this->len = 0; this->addr = 0; } diff --git a/firrtl b/firrtl index 5581e780..16839288 160000 --- a/firrtl +++ b/firrtl @@ -1 +1 @@ -Subproject commit 5581e78092b39d73430b566c694eeebae1ad3741 +Subproject commit 168392889d42506fae5a1aa637ebe1e61d799e62 diff --git a/groundtest b/groundtest index 99b96511..b2fb2cd9 160000 --- a/groundtest +++ b/groundtest @@ -1 +1 @@ -Subproject commit 99b96511f7237760fb2552cb8a8f2f569adb78f5 +Subproject commit b2fb2cd969619433a2c67ee6dad6c4b84206ee14 diff --git a/junctions b/junctions index a43e687a..4c2d3749 160000 --- a/junctions +++ b/junctions @@ -1 +1 @@ -Subproject commit a43e687ad03708d367f86cb7bc13f66431b1d442 +Subproject commit 4c2d3749a742f4a6389cdedfd51da4a3cfa00f76 diff --git a/rocket b/rocket index c611fb05..f519082f 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit c611fb05f342ed817126bce64b16e3abbbf369de +Subproject commit f519082ff320f34ae7971c5590c8c8a919857cf4 diff --git a/src/main/scala/TestBench.scala b/src/main/scala/TestBench.scala index cf22582c..664fab84 100644 --- a/src/main/scala/TestBench.scala +++ b/src/main/scala/TestBench.scala @@ -300,15 +300,15 @@ object TestBenchGeneration extends FileSystemUtilities { begin if (ar_valid_$i && ar_ready_$i) begin - $$fdisplay(stderr, "MC$i: ar addr=%x", ar_addr_$i); + $$fdisplay(stderr, "MC$i: ar addr=%x size=%x", ar_addr_$i, ar_size_$i); end if (aw_valid_$i && aw_ready_$i) begin - $$fdisplay(stderr, "MC$i: aw addr=%x", aw_addr_$i); + $$fdisplay(stderr, "MC$i: aw addr=%x size=%x", aw_addr_$i, aw_size_$i); end if (w_valid_$i && w_ready_$i) begin - $$fdisplay(stderr, "MC$i: w data=%x", w_data_$i); + $$fdisplay(stderr, "MC$i: w data=%x strb=%x", w_data_$i, w_strb_$i); end if (r_valid_$i && r_ready_$i) begin diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala index 869e4b66..a2f36612 100644 --- a/src/main/scala/TestConfigs.scala +++ b/src/main/scala/TestConfigs.scala @@ -142,7 +142,7 @@ class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig) class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new WithTraceGen ++ new GroundTestConfig) class FancyMemtestConfig extends Config( - new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++ + new With2Cores ++ new With2MemoryChannels ++ new With4BanksPerMemChannel ++ new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig) class MemoryMuxMemtestConfig extends Config( diff --git a/uncore b/uncore index a5d2d539..82cc100d 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit a5d2d539682c4013585a99e3472e295df5507ea9 +Subproject commit 82cc100db1ef37826d00595b0969a70e5c9dd7e1