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Fix narrow read/write behavior for AXI converters and fix L2 bugs

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Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
This commit is contained in:
Howard Mao
2016-04-01 17:53:59 -07:00
parent c4c6bd1040
commit c5838dd9b3
13 changed files with 27 additions and 29 deletions
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6
src/main/scala/TestBench.scala
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@ -300,15 +300,15 @@ object TestBenchGeneration extends FileSystemUtilities {
begin
if (ar_valid_$i && ar_ready_$i)
begin
$$fdisplay(stderr, "MC$i: ar addr=%x", ar_addr_$i);
$$fdisplay(stderr, "MC$i: ar addr=%x size=%x", ar_addr_$i, ar_size_$i);
end
if (aw_valid_$i && aw_ready_$i)
begin
$$fdisplay(stderr, "MC$i: aw addr=%x", aw_addr_$i);
$$fdisplay(stderr, "MC$i: aw addr=%x size=%x", aw_addr_$i, aw_size_$i);
end
if (w_valid_$i && w_ready_$i)
begin
$$fdisplay(stderr, "MC$i: w data=%x", w_data_$i);
$$fdisplay(stderr, "MC$i: w data=%x strb=%x", w_data_$i, w_strb_$i);
end
if (r_valid_$i && r_ready_$i)
begin

2
src/main/scala/TestConfigs.scala
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@ -142,7 +142,7 @@ class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new WithTraceGen ++ new GroundTestConfig)
class FancyMemtestConfig extends Config(
new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
new With2Cores ++ new With2MemoryChannels ++ new With4BanksPerMemChannel ++
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
class MemoryMuxMemtestConfig extends Config(