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Fix narrow read/write behavior for AXI converters and fix L2 bugs

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Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
This commit is contained in:
Howard Mao
2016-04-01 17:53:59 -07:00
parent c4c6bd1040
commit c5838dd9b3
13 changed files with 27 additions and 29 deletions
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5
csrc/mm_dramsim2.h
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@ -11,14 +11,12 @@
struct mm_req_t {
uint64_t id;
uint64_t size;
uint64_t len;
uint64_t addr;
mm_req_t(uint64_t id, uint64_t size, uint64_t len, uint64_t addr)
mm_req_t(uint64_t id, uint64_t len, uint64_t addr)
{
this->id = id;
this->size = size;
this->len = len;
this->addr = addr;
}
@ -26,7 +24,6 @@ struct mm_req_t {
mm_req_t()
{
this->id = 0;
this->size = 0;
this->len = 0;
this->addr = 0;
}