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Fix narrow read/write behavior for AXI converters and fix L2 bugs

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Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
This commit is contained in:
Howard Mao
2016-04-01 17:53:59 -07:00
parent c4c6bd1040
commit c5838dd9b3
13 changed files with 27 additions and 29 deletions
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5
csrc/mm.h
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@ -7,9 +7,6 @@
#include <cstring>
#include <queue>
void write_masked_data(
uint8_t *base, uint8_t *data, uint64_t strb, uint64_t size);
class mm_t
{
public:
@ -58,7 +55,7 @@ class mm_t
virtual size_t get_line_size() { return line_size; }
void write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size);
std::vector<char> read(uint64_t addr, uint64_t size);
std::vector<char> read(uint64_t addr);
virtual ~mm_t();