riscv/rocket-chip
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reverse order of RWX bits for compatibility

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This commit is contained in:
Howard Mao 2015-12-05 00:26:16 -08:00
parent 7083576156
commit c57639b23f
1 changed files with 4 additions and 4 deletions
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8
junctions/src/main/scala/addrmap.scala
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@ -40,18 +40,18 @@ case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion
case class MemChannels(size: BigInt, nchannels: Int, prot: Int) extends MemRegion case class MemChannels(size: BigInt, nchannels: Int, prot: Int) extends MemRegion
object AddrMapConsts { object AddrMapConsts {
val R = 0x4 val R = 0x1
val W = 0x2 val W = 0x2
val X = 0x1 val X = 0x4
val RW = R | W val RW = R | W
val RX = R | X val RX = R | X
val RWX = R | W | X val RWX = R | W | X
} }
class AddrMapProt extends Bundle { class AddrMapProt extends Bundle {
val r = Bool()
val w = Bool()
val x = Bool() val x = Bool()
val w = Bool()
val r = Bool()
} }
case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion) case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion)