riscv/rocket-chip
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[rocket] use more standard pattern for computing integer min

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This commit is contained in:
Andrew Waterman 2016-07-29 15:19:09 -07:00
parent ffac86b041
commit c465120610
2 changed files with 1 additions and 7 deletions
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2
rocket/src/main/scala/dma.scala
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@ -125,7 +125,7 @@ class DmaFrontend(implicit p: Parameters) extends CoreModule()(p)
val last_src_vpn = Reg(UInt(width = vpnBits)) val last_src_vpn = Reg(UInt(width = vpnBits))
val last_dst_vpn = Reg(UInt(width = vpnBits)) val last_dst_vpn = Reg(UInt(width = vpnBits))
val tx_len = Util.minUInt(src_pglen, dst_pglen, bytes_left) val tx_len = src_pglen min dst_pglen min bytes_left
val dma_busy = Reg(init = UInt(0, tlMaxClientXacts)) val dma_busy = Reg(init = UInt(0, tlMaxClientXacts))
val dma_xact_id = PriorityEncoder(~dma_busy) val dma_xact_id = PriorityEncoder(~dma_busy)

6
rocket/src/main/scala/util.scala
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@ -44,12 +44,6 @@ object Util {
def toBits(): UInt = Cat(x.map(_.toBits).reverse) def toBits(): UInt = Cat(x.map(_.toBits).reverse)
} }
def minUInt(values: Seq[UInt]): UInt =
values.reduce((a, b) => Mux(a < b, a, b))
def minUInt(first: UInt, rest: UInt*): UInt =
minUInt(first +: rest.toSeq)
implicit class UIntIsOneOf(val x: UInt) extends AnyVal { implicit class UIntIsOneOf(val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_) def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_)