Move PRCI from Coreplex to always-on block, where it belongs

src/main/scala/coreplex/Coreplex.scala

@@ -59,7 +59,7 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
     val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
     val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
     val debug = new DebugBusIO()(p).flip
-    val rtcTick = Bool(INPUT)
+    val prci = Vec(c.nTiles, new PRCITileIO).flip
     val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
   }
 
@@ -170,14 +170,10 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
     debugModule.io.tl <> mmioNetwork.port("int:debug")
     debugModule.io.db <> io.debug
 
-    val prci = Module(new PRCI)
-    prci.io.tl <> mmioNetwork.port("int:prci")
-    prci.io.rtcTick := io.rtcTick
-
     // connect coreplex-internal interrupts to tiles
     for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) {
-      tileReset := prci.io.tiles(i).reset
+      tileReset := io.prci(i).reset
-      tile.io.interrupts := prci.io.tiles(i).interrupts
+      tile.io.interrupts := io.prci(i).interrupts
       tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
       tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
       tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)

src/main/scala/rocketchip/Periphery.scala

@@ -276,6 +276,33 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
 
 /////
 
+/** Always-ON block */
+trait PeripheryAON extends LazyModule {
+  implicit val p: Parameters
+  val pDevices: ResourceManager[AddrMapEntry]
+
+  pDevices.add(AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW))))
+}
+
+trait PeripheryAONBundle {
+  implicit val p: Parameters
+}
+
+trait PeripheryAONModule extends HasPeripheryParameters {
+  implicit val p: Parameters
+  val outer: PeripheryAON
+  val io: PeripheryAONBundle
+  val mmioNetwork: Option[TileLinkRecursiveInterconnect]
+  val coreplex: Coreplex
+
+  val prci = Module(new PRCI()(innerMMIOParams))
+  prci.io.rtcTick := Counter(p(RTCPeriod)).inc()
+  prci.io.tl <> mmioNetwork.get.port("prci")
+  coreplex.io.prci <> prci.io.tiles
+}
+
+/////
+
 trait PeripheryTestRAM extends LazyModule {
   implicit val p: Parameters
   val pDevices: ResourceManager[AddrMapEntry]

src/main/scala/rocketchip/Top.scala

@@ -66,7 +66,6 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   val io: B = b(coreplex)
 
   io.success zip coreplex.io.success map { case (x, y) => x := y }
-  coreplex.io.rtcTick := Counter(p(RTCPeriod)).inc()
 
   val mmioNetwork = c.hasExtMMIOPort.option(
     Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(
@@ -76,17 +75,17 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
 
 /** Example Top with Periphery */
 class ExampleTop(p: Parameters) extends BaseTop(p)
-    with PeripheryDebug with PeripheryExtInterrupts
+    with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
     with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
   override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
 }
 
 class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
-    with PeripheryDebugBundle with PeripheryExtInterruptsBundle
+    with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
     with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
 
 class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
-    with PeripheryDebugModule with PeripheryExtInterruptsModule
+    with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
     with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
 
 /** Example Top with TestRAM */

src/main/scala/rocketchip/Utils.scala

@@ -54,7 +54,6 @@ object GenerateGlobalAddrMap {
       entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
       entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
       entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
-      entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
       if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
         require(p(NTiles) == 1) // TODO relax this
         require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM
@@ -84,7 +83,7 @@ object GenerateConfigString {
   def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
     val addrMap = p(GlobalAddrMap).get
     val plicAddr = addrMap("io:int:plic").start
-    val prciAddr = addrMap("io:int:prci").start
+    val prciAddr = addrMap("io:ext:prci").start
     val xLen = p(XLen)
     val res = new StringBuilder
     res append  "plic {\n"