riscv/rocket-chip
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Move PRCI from Coreplex to always-on block, where it belongs

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This commit is contained in:
Andrew Waterman
2016-09-14 10:57:01 -07:00
parent 5566bf1b13
commit c3ddff809b
4 changed files with 34 additions and 13 deletions
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27
src/main/scala/rocketchip/Periphery.scala
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@ -276,6 +276,33 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
/////
/** Always-ON block */
trait PeripheryAON extends LazyModule {
implicit val p: Parameters
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW))))
}
trait PeripheryAONBundle {
implicit val p: Parameters
}
trait PeripheryAONModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryAON
val io: PeripheryAONBundle
val mmioNetwork: Option[TileLinkRecursiveInterconnect]
val coreplex: Coreplex
val prci = Module(new PRCI()(innerMMIOParams))
prci.io.rtcTick := Counter(p(RTCPeriod)).inc()
prci.io.tl <> mmioNetwork.get.port("prci")
coreplex.io.prci <> prci.io.tiles
}
/////
trait PeripheryTestRAM extends LazyModule {
implicit val p: Parameters
val pDevices: ResourceManager[AddrMapEntry]

7
src/main/scala/rocketchip/Top.scala
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@ -66,7 +66,6 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
val io: B = b(coreplex)
io.success zip coreplex.io.success map { case (x, y) => x := y }
coreplex.io.rtcTick := Counter(p(RTCPeriod)).inc()
val mmioNetwork = c.hasExtMMIOPort.option(
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(
@ -76,17 +75,17 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
/** Example Top with Periphery */
class ExampleTop(p: Parameters) extends BaseTop(p)
with PeripheryDebug with PeripheryExtInterrupts
with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
}
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
with PeripheryDebugBundle with PeripheryExtInterruptsBundle
with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
with PeripheryDebugModule with PeripheryExtInterruptsModule
with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
/** Example Top with TestRAM */

3
src/main/scala/rocketchip/Utils.scala
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@ -54,7 +54,6 @@ object GenerateGlobalAddrMap {
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
require(p(NTiles) == 1) // TODO relax this
require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM
@ -84,7 +83,7 @@ object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
val addrMap = p(GlobalAddrMap).get
val plicAddr = addrMap("io:int:plic").start
val prciAddr = addrMap("io:int:prci").start
val prciAddr = addrMap("io:ext:prci").start
val xLen = p(XLen)
val res = new StringBuilder
res append "plic {\n"