riscv/rocket-chip
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Chisel3: Flip order of := and <>

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This commit is contained in:
Andrew Waterman 2015-08-03 18:52:59 -07:00
parent ef319edc84
commit c345d72af4
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -830,8 +830,8 @@ class HellaCache extends L1HellaCacheModule {
writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en
writeArb.io.in(1).bits.wmask := ~UInt(0, nWays) writeArb.io.in(1).bits.wmask := ~UInt(0, nWays)
writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0) writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0)
readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked
data.io.read <> readArb.io.out data.io.read <> readArb.io.out
readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked
// writebacks // writebacks
val wbArb = Module(new Arbiter(new WritebackReq, 2)) val wbArb = Module(new Arbiter(new WritebackReq, 2))