From c345d72af4bfdf490b1d552ab19ed79b1a351e0c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 3 Aug 2015 18:52:59 -0700 Subject: [PATCH] Chisel3: Flip order of := and <> --- rocket/src/main/scala/nbdcache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 0ff9a50a..ac48b7b3 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -830,8 +830,8 @@ class HellaCache extends L1HellaCacheModule { writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en writeArb.io.in(1).bits.wmask := ~UInt(0, nWays) writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0) - readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked data.io.read <> readArb.io.out + readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked // writebacks val wbArb = Module(new Arbiter(new WritebackReq, 2))