riscv/rocket-chip
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If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.

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This commit is contained in:
Megan Wachs 2016-07-18 14:12:22 -07:00 committed by Howard Mao
parent ffe17cbb2b
commit c31c650def
2 changed files with 14 additions and 3 deletions
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13
src/main/scala/Configs.scala
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@ -256,7 +256,9 @@ class BaseConfig extends Config (
dataBits = site(XLen)) dataBits = site(XLen))
case TLKey("L1toL2") => case TLKey("L1toL2") =>
TileLinkParameters( TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)), coherencePolicy = (if (site(NTiles) == 1)
new MEICoherence(site(L2DirectoryRepresentation)) else
new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */, nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts), nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts), nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
@ -379,6 +381,15 @@ class WithBufferlessBroadcastHub extends Config(
case OuterTLId => "L2toMC" }))) case OuterTLId => "L2toMC" })))
}) })
class WithStatelessBridge extends Config (
(pname, site, here) => pname match {
case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
Module(new ManagerToClientStatelessBridge()(p.alterPartial({
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMC" })))
}
)
class WithPLRU extends Config( class WithPLRU extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays)) case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))

2
uncore

@ -1 +1 @@
Subproject commit ec22e086e5ce4378d8085a4384b2acc7c465bfab Subproject commit b4092a6ff8021b0e57ab5ce8c11ef6a6dafec1fb