diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 7eae3bd0..aa27f7e5 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -254,9 +254,11 @@ class BaseConfig extends Config (
         HastiParameters(
           addrBits = site(PAddrBits),
           dataBits = site(XLen))
-      case TLKey("L1toL2") => 
+      case TLKey("L1toL2") =>
         TileLinkParameters(
-          coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
+          coherencePolicy = (if (site(NTiles) == 1)
+            new MEICoherence(site(L2DirectoryRepresentation)) else
+              new MESICoherence(site(L2DirectoryRepresentation))),
           nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
           nCachingClients = site(NCachedTileLinkPorts),
           nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
@@ -379,6 +381,15 @@ class WithBufferlessBroadcastHub extends Config(
         case OuterTLId => "L2toMC" })))
   })
 
+class WithStatelessBridge extends Config (
+  (pname, site, here) => pname match {
+    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
+      Module(new ManagerToClientStatelessBridge()(p.alterPartial({
+        case InnerTLId => "L1toL2"
+        case OuterTLId => "L2toMC" })))
+  }
+)
+
 class WithPLRU extends Config(
   (pname, site, here) => pname match {
     case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
diff --git a/uncore b/uncore
index ec22e086..b4092a6f 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit ec22e086e5ce4378d8085a4384b2acc7c465bfab
+Subproject commit b4092a6ff8021b0e57ab5ce8c11ef6a6dafec1fb