riscv/rocket-chip
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Merge pull request #996 from freechipsproject/fix-dcache-bug

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Only merge stores that aren't yet pending
This commit is contained in:
Yunsup Lee 2017-09-17 15:59:32 -07:00 committed by GitHub
commit c24b275fd9
1 changed files with 2 additions and 2 deletions
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src/main/scala/rocket/DCache.scala
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@ -294,6 +294,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid) && Bool(usingDataScratchpad) val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid) && Bool(usingDataScratchpad)
// pending store buffer // pending store buffer
val s2_valid_correct = s2_valid_hit_pre_data_ecc && s2_correct val s2_valid_correct = s2_valid_hit_pre_data_ecc && s2_correct
val s2_store_valid = s2_valid_hit && s2_write && !s2_sc_fail
val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write)
val pstore1_addr = RegEnable(s1_paddr, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_paddr, s1_valid_not_nacked && s1_write)
val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write)
@ -302,7 +303,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val pstore1_storegen_data = Wire(init = pstore1_data) val pstore1_storegen_data = Wire(init = pstore1_data)
val pstore1_rmw = Bool(usingRMW) && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_rmw = Bool(usingRMW) && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write)
val pstore1_valid = Wire(Bool()) val pstore1_valid = Wire(Bool())
val pstore1_merge = pstore1_valid && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge
val pstore2_valid = Reg(Bool()) val pstore2_valid = Reg(Bool())
any_pstore_valid := pstore1_valid || pstore2_valid any_pstore_valid := pstore1_valid || pstore2_valid
val pstore_drain_structural = pstore1_valid && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw) val pstore_drain_structural = pstore1_valid && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw)
@ -312,7 +313,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
(Bool(usingRMW) && pstore_drain_structural || (Bool(usingRMW) && pstore_drain_structural ||
(((pstore1_valid && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))) (((pstore1_valid && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss)))
pstore1_valid := { pstore1_valid := {
val s2_store_valid = s2_valid_hit && s2_write && !s2_sc_fail
val pstore1_held = Reg(Bool()) val pstore1_held = Reg(Bool())
assert(!s2_store_valid || !pstore1_held) assert(!s2_store_valid || !pstore1_held)
pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain