1
0

add an L1 cache request generator

This commit is contained in:
Howard Mao 2015-10-30 12:49:57 -07:00
parent 3103fa8da2
commit c1f42ce3d4
2 changed files with 73 additions and 9 deletions

View File

@ -3,6 +3,7 @@ package groundtest
import Chisel._
import uncore._
import junctions._
import rocket._
import scala.util.Random
import cde.{Parameters, Field}
@ -20,7 +21,7 @@ class UncachedTileLinkGenerator(id: Int)
(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt
private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt / 2
private val totalRequests = maxAddress / nGens
val io = new Bundle {
@ -81,6 +82,54 @@ class UncachedTileLinkGenerator(id: Int)
assert(!io.mem.grant.valid || state != s_get ||
io.mem.grant.bits.data === get_data,
s"Get received incorrect data in generator ${id}")
s"Get received incorrect data in uncached generator ${id}")
}
class HellaCacheGenerator(id: Int)
(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParams {
private val wordOffset = log2Up(coreDataBits / 8)
private val maxAddress = (p(MMIOBase) >> wordOffset).toInt
private val startAddress = maxAddress / 2
private val totalRequests = (maxAddress - startAddress) / nGens
val io = new Bundle {
val finished = Bool(OUTPUT)
val mem = new HellaCacheIO
}
val (s_start :: s_write :: s_read :: s_finished :: Nil) = Enum(Bits(), 4)
val state = Reg(init = s_start)
val sending = Reg(init = Bool(false))
val (req_cnt, req_wrap) = Counter(
io.mem.resp.valid && io.mem.resp.bits.has_data, totalRequests)
val req_addr = UInt(startAddress) +
Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset))
val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, req_addr)
io.mem.req.valid := sending
io.mem.req.bits.addr := req_addr
io.mem.req.bits.data := req_data
io.mem.req.bits.typ := MT_D
io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
io.mem.req.bits.tag := UInt(0)
io.mem.req.bits.kill := Bool(false)
io.mem.req.bits.phys := Bool(true)
when (state === s_start) { sending := Bool(true); state := s_write }
when (io.mem.req.fire()) { sending := Bool(false) }
when (io.mem.resp.valid) {
sending := Bool(true)
state := Mux(state === s_write, s_read, s_write)
}
when (req_wrap) { sending := Bool(false); state := s_finished }
assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data ||
io.mem.resp.bits.data === req_data,
s"Received incorrect data in cached generator ${id}")
}

View File

@ -36,19 +36,34 @@ class DummyCache(implicit val p: Parameters) extends Module
class GeneratorTile(id: Int, resetSignal: Bool)
(implicit val p: Parameters) extends Tile(resetSignal)(p)
with HasGeneratorParams {
val gen_finished = Wire(Vec(nGensPerTile, Bool()))
val arb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
val gen_finished = Wire(Vec(2 * nGensPerTile, Bool()))
val uncacheArb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
val cacheArb = Module(new HellaCacheArbiter(nGensPerTile)(dcacheParams))
val cache = Module(new HellaCache()(dcacheParams))
for (i <- 0 until nGensPerTile) {
val genid = id * nGensPerTile + i
val generator = Module(new UncachedTileLinkGenerator(genid))
arb.io.in(i) <> generator.io.mem
gen_finished(i) := generator.io.finished
val uncacheGen = Module(new UncachedTileLinkGenerator(genid))
val cacheGen = Module(new HellaCacheGenerator(genid)(dcacheParams))
val cacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
uncacheArb.io.in(i) <> uncacheGen.io.mem
cacheIF.io.requestor <> cacheGen.io.mem
cacheArb.io.requestor(i) <> cacheIF.io.cache
gen_finished(2 * i) := uncacheGen.io.finished
gen_finished(2 * i + 1) := cacheGen.io.finished
}
io.uncached(0) <> arb.io.out
io.cached(0) <> Module(new DummyCache).io
cache.io.ptw.req.ready := Bool(false)
cache.io.ptw.resp.valid := Bool(false)
cache.io.cpu <> cacheArb.io.mem
assert(!cache.io.ptw.req.valid,
"Cache should not be using virtual addressing")
io.uncached(0) <> uncacheArb.io.out
io.cached(0) <> cache.io.mem
val all_done = gen_finished.reduce(_ && _)