riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Revert "add new parameters for new SCR file"

Browse Source 
This reverts commit 4dad5b8b32.

The commit breaks the build.
This commit is contained in:
Christopher Celio
2016-02-13 04:02:20 -08:00
parent 6c6bbca92a
commit c1b4d9372f
2 changed files with 0 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/Configs.scala
View File

@@ -75,11 +75,9 @@ class DefaultConfig extends Config (
case HtifKey => HtifParameters( case HtifKey => HtifParameters(
width = Dump("HTIF_WIDTH", 16), width = Dump("HTIF_WIDTH", 16),
nSCR = 64, nSCR = 64,
nUncoreSCR = 64,
csrDataBits = site(XLen), csrDataBits = site(XLen),
offsetBits = site(CacheBlockOffsetBits), offsetBits = site(CacheBlockOffsetBits),
nCores = site(NTiles)) nCores = site(NTiles))
case GlobalScrMap => new ScrMap
//Memory Parameters //Memory Parameters
case PAddrBits => 32 case PAddrBits => 32
case PgIdxBits => 12 case PgIdxBits => 12

1
src/main/scala/RocketChip.scala
View File

@@ -53,7 +53,6 @@ trait HasTopLevelParameters {
lazy val mifDataBeats = p(MIFDataBeats) lazy val mifDataBeats = p(MIFDataBeats)
lazy val xLen = p(XLen) lazy val xLen = p(XLen)
lazy val nSCR = p(HtifKey).nSCR lazy val nSCR = p(HtifKey).nSCR
lazy val nUncoreSCR = p(HtifKey).nUncoreSCR
lazy val scrAddrBits = log2Up(nSCR) lazy val scrAddrBits = log2Up(nSCR)
lazy val scrDataBits = 64 lazy val scrDataBits = 64
lazy val scrDataBytes = scrDataBits / 8 lazy val scrDataBytes = scrDataBits / 8