From c1b4d9372fe26f2d58901fac7e03756e655d859c Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Sat, 13 Feb 2016 04:02:20 -0800 Subject: [PATCH] Revert "add new parameters for new SCR file" This reverts commit 4dad5b8b32dac06601cfff1d048eadcc30a8873b. The commit breaks the build. --- src/main/scala/Configs.scala | 2 -- src/main/scala/RocketChip.scala | 1 - 2 files changed, 3 deletions(-) diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 60ef62a4..a0b66f30 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -75,11 +75,9 @@ class DefaultConfig extends Config ( case HtifKey => HtifParameters( width = Dump("HTIF_WIDTH", 16), nSCR = 64, - nUncoreSCR = 64, csrDataBits = site(XLen), offsetBits = site(CacheBlockOffsetBits), nCores = site(NTiles)) - case GlobalScrMap => new ScrMap //Memory Parameters case PAddrBits => 32 case PgIdxBits => 12 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index fbcb2d51..3e1efeaf 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -53,7 +53,6 @@ trait HasTopLevelParameters { lazy val mifDataBeats = p(MIFDataBeats) lazy val xLen = p(XLen) lazy val nSCR = p(HtifKey).nSCR - lazy val nUncoreSCR = p(HtifKey).nUncoreSCR lazy val scrAddrBits = log2Up(nSCR) lazy val scrDataBits = 64 lazy val scrDataBytes = scrDataBits / 8