riscv/rocket-chip
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TLB: determine RWX from TL2 properties directly

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This commit is contained in:
Wesley W. Terpstra
2016-11-21 11:48:10 -08:00
parent 3d1a7bd6d3
commit c18bc07bbc
6 changed files with 42 additions and 28 deletions
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17
src/main/scala/rocket/tile.scala
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@ -24,12 +24,15 @@ case class RoccParameters(
useFPU: Boolean = false)
class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val dcacheParams = p.alterPartial({
val coreParams = p.alterPartial {
case TLCacheEdge => cachedOut.edgesOut(0)
}
val dcacheParams = coreParams.alterPartial({
case CacheName => CacheName("L1D")
case TLId => "L1toL2"
case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid?
})
val icacheParams = p.alterPartial({
val icacheParams = coreParams.alterPartial({
case CacheName => CacheName("L1I")
case TLId => "L1toL2"
})
@ -54,7 +57,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val uncached = uncachedOut.bundleOut
val slave = slaveNode.map(_.bundleIn)
val hartid = UInt(INPUT, p(XLen))
val interrupts = new TileInterrupts().asInput
val interrupts = new TileInterrupts()(coreParams).asInput
val resetVector = UInt(INPUT, p(XLen))
}
@ -74,15 +77,15 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
icache.io.cpu <> core.io.imem
icache.io.resetVector := io.resetVector
val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)))
val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)(coreParams)))
fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
if (usingRocc) {
val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
val respArb = Module(new RRArbiter(new RoCCResponse()(coreParams), nRocc))
core.io.rocc.resp <> respArb.io.out
val roccOpcodes = buildRocc.map(_.opcodes)
val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)(coreParams))
cmdRouter.io.in <> core.io.rocc.cmd
val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
@ -101,7 +104,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
if (nFPUPorts > 0) {
fpuOpt.foreach { fpu =>
val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
val fpArb = Module(new InOrderArbiter(new FPInput()(coreParams), new FPResult()(coreParams), nFPUPorts))
val fp_roccs = roccs.zip(buildRocc)
.filter { case (_, params) => params.useFPU }
.map { case (rocc, _) => rocc.io }