diff --git a/src/main/scala/rocket/Dcache.scala b/src/main/scala/rocket/Dcache.scala
index 4c44943f..5f91dee6 100644
--- a/src/main/scala/rocket/Dcache.scala
+++ b/src/main/scala/rocket/Dcache.scala
@@ -123,7 +123,7 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu
       require(nWays == 1)
       metaWriteArb.io.out.ready := true
       metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
-      val inScratchpad = addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr)
+      val inScratchpad = Bool(false) // !!! addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr)
       val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
       (inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
     } else {
diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala
index eb1a91f9..f8d3145b 100644
--- a/src/main/scala/rocket/HellaCache.scala
+++ b/src/main/scala/rocket/HellaCache.scala
@@ -145,7 +145,6 @@ class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends La
     with HasL1HellaCacheParameters {
   implicit val cfg = outer.cfg
   val io = new HellaCacheBundle(outer)
-  val edge = outer.node.edgesOut(0)
   val tl_out = io.mem(0)
 
   /* TODO
diff --git a/src/main/scala/rocket/csr.scala b/src/main/scala/rocket/csr.scala
index 4c67d2c2..82f59310 100644
--- a/src/main/scala/rocket/csr.scala
+++ b/src/main/scala/rocket/csr.scala
@@ -8,7 +8,6 @@ import config._
 import uncore.devices._
 import util._
 import Chisel.ImplicitConversions._
-import junctions.AddrMap
 
 class MStatus extends Bundle {
   // not truly part of mstatus, but convenient
diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala
index ea350c84..7413d9b5 100644
--- a/src/main/scala/rocket/rocket.scala
+++ b/src/main/scala/rocket/rocket.scala
@@ -6,7 +6,7 @@ import Chisel._
 import uncore.devices._
 import uncore.agents.CacheName
 import uncore.constants._
-import junctions.HasAddrMapParameters
+import uncore.tilelink2._
 import util._
 import Chisel.ImplicitConversions._
 import config._
@@ -32,12 +32,14 @@ case object NBreakpoints extends Field[Int]
 case object NPerfCounters extends Field[Int]
 case object NPerfEvents extends Field[Int]
 case object DataScratchpadSize extends Field[Int]
+case object TLCacheEdge extends Field[TLEdgeOut]
 
-trait HasCoreParameters extends HasAddrMapParameters {
+trait HasCoreParameters {
   implicit val p: Parameters
   val xLen = p(XLen)
   val fLen = xLen // TODO relax this
 
+  val edge = p(TLCacheEdge)
   val usingVM = p(UseVM)
   val usingUser = p(UseUser) || usingVM
   val usingDebug = p(UseDebug)
@@ -67,6 +69,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
   def pgIdxBits = 12
   def pgLevelBits = 10 - log2Ceil(xLen / 32)
   def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
+  val paddrBits = edge.bundle.addressBits
   def ppnBits = paddrBits - pgIdxBits
   def vpnBits = vaddrBits - pgIdxBits
   val pgLevels = p(PgLevels)
diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala
index 1ebc8836..6d0f4109 100644
--- a/src/main/scala/rocket/tile.scala
+++ b/src/main/scala/rocket/tile.scala
@@ -24,12 +24,15 @@ case class RoccParameters(
   useFPU: Boolean = false)
 
 class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
-  val dcacheParams = p.alterPartial({
+  val coreParams = p.alterPartial {
+    case TLCacheEdge => cachedOut.edgesOut(0)
+  }
+  val dcacheParams = coreParams.alterPartial({
     case CacheName => CacheName("L1D")
     case TLId => "L1toL2"
     case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid?
   })
-  val icacheParams = p.alterPartial({
+  val icacheParams = coreParams.alterPartial({
     case CacheName => CacheName("L1I")
     case TLId => "L1toL2"
   })
@@ -54,7 +57,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
       val uncached = uncachedOut.bundleOut
       val slave = slaveNode.map(_.bundleIn)
       val hartid = UInt(INPUT, p(XLen))
-      val interrupts = new TileInterrupts().asInput
+      val interrupts = new TileInterrupts()(coreParams).asInput
       val resetVector = UInt(INPUT, p(XLen))
     }
 
@@ -74,15 +77,15 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
     icache.io.cpu <> core.io.imem
     icache.io.resetVector := io.resetVector
 
-    val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)))
+    val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)(coreParams)))
     fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
 
     if (usingRocc) {
-      val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
+      val respArb = Module(new RRArbiter(new RoCCResponse()(coreParams), nRocc))
       core.io.rocc.resp <> respArb.io.out
 
       val roccOpcodes = buildRocc.map(_.opcodes)
-      val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
+      val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)(coreParams))
       cmdRouter.io.in <> core.io.rocc.cmd
 
       val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
@@ -101,7 +104,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
 
       if (nFPUPorts > 0) {
         fpuOpt.foreach { fpu =>
-          val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
+          val fpArb = Module(new InOrderArbiter(new FPInput()(coreParams), new FPResult()(coreParams), nFPUPorts))
           val fp_roccs = roccs.zip(buildRocc)
             .filter { case (_, params) => params.useFPU }
             .map { case (rocc, _) => rocc.io }
diff --git a/src/main/scala/rocket/tlb.scala b/src/main/scala/rocket/tlb.scala
index 339f2e84..86020004 100644
--- a/src/main/scala/rocket/tlb.scala
+++ b/src/main/scala/rocket/tlb.scala
@@ -5,17 +5,19 @@ package rocket
 import Chisel._
 import util._
 import Chisel.ImplicitConversions._
-import junctions._
 import scala.math._
 import config._
+import diplomacy._
 import uncore.agents._
 import uncore.coherence._
+import uncore.tilelink2._
 
 case object PgLevels extends Field[Int]
 case object ASIdBits extends Field[Int]
 
 trait HasTLBParameters extends HasCoreParameters {
   val entries = p(p(CacheName)).nTLBEntries
+  val cacheBlockBytes = p(CacheBlockBytes)
   val camAddrBits = log2Ceil(entries)
   val camTagBits = asIdBits + vpnBits
 }
@@ -64,15 +66,23 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
   val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
   val do_refill = Bool(usingVM) && io.ptw.resp.valid
   val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
-  val prot = addrMap.getProt(mpu_ppn << pgIdxBits)
-  val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits)
-  def pgaligned(r: MemRegion) = {
-    val pgsize = 1 << pgIdxBits
-    (r.start % pgsize) == 0 && (r.size % pgsize) == 0
+  def fastCheck(member: TLManagerParameters => Boolean) =
+    Mux1H(edge.manager.findFast(mpu_ppn << pgIdxBits), edge.manager.managers.map(m => Bool(member(m))))
+  val prot_r = fastCheck(_.supportsGet)
+  val prot_w = fastCheck(_.supportsPutFull)
+  val prot_x = fastCheck(_.executable)
+  val cacheable = fastCheck(_.supportsAcquire)
+  val allSizes = TransferSizes(1, cacheBlockBytes)
+  val amoSizes = TransferSizes(1, xLen/8)
+  edge.manager.managers.foreach { m =>
+    require (m.minAlignment >= 4096, s"MemoryMap region ${m.name} must be page-aligned (is ${m.minAlignment})")
+    require (!m.supportsGet     || m.supportsGet    .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsGet} Get, but must support ${allSizes}")
+    require (!m.supportsPutFull || m.supportsPutFull.contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
+    require (!m.supportsAcquire || m.supportsAcquire.contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquire} Acquire, but must support ${allSizes}")
+    require (!m.supportsLogical || m.supportsLogical.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
+    require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
   }
-  require(addrMap.flatten.forall(e => pgaligned(e.region)),
-    "MemoryMap regions must be page-aligned")
-  
+
   val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
   val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
   val hitsVec = (0 until entries).map(i => valid(i) && vm_enabled && tags(i) === lookup_tag) :+ !vm_enabled
@@ -95,10 +105,10 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
     val mask = UIntToOH(r_refill_waddr)
     valid := valid | mask
     u_array := Mux(pte.u, u_array | mask, u_array & ~mask)
-    sw_array := Mux(pte.sw() && prot.w, sw_array | mask, sw_array & ~mask)
-    sx_array := Mux(pte.sx() && prot.x, sx_array | mask, sx_array & ~mask)
-    sr_array := Mux(pte.sr() && prot.r, sr_array | mask, sr_array & ~mask)
-    xr_array := Mux(pte.sx() && prot.r, xr_array | mask, xr_array & ~mask)
+    sw_array := Mux(pte.sw() && prot_w, sw_array | mask, sw_array & ~mask)
+    sx_array := Mux(pte.sx() && prot_x, sx_array | mask, sx_array & ~mask)
+    sr_array := Mux(pte.sr() && prot_r, sr_array | mask, sr_array & ~mask)
+    xr_array := Mux(pte.sx() && prot_r, xr_array | mask, xr_array & ~mask)
     cash_array := Mux(cacheable, cash_array | mask, cash_array & ~mask)
     dirty_array := Mux(pte.d, dirty_array | mask, dirty_array & ~mask)
   }
@@ -107,9 +117,9 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
   val repl_waddr = Mux(!valid.andR, PriorityEncoder(~valid), plru.replace)
 
   val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.pum, u_array, UInt(0)), u_array)
-  val w_array = Cat(prot.w, priv_ok & sw_array)
-  val x_array = Cat(prot.x, priv_ok & sx_array)
-  val r_array = Cat(prot.r, priv_ok & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0))))
+  val w_array = Cat(prot_w, priv_ok & sw_array)
+  val x_array = Cat(prot_x, priv_ok & sx_array)
+  val r_array = Cat(prot_r, priv_ok & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0))))
   val c_array = Cat(cacheable, cash_array)
 
   val bad_va =