riscv/rocket-chip
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TLB: determine RWX from TL2 properties directly

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This commit is contained in:
Wesley W. Terpstra
2016-11-21 11:48:10 -08:00
parent 3d1a7bd6d3
commit c18bc07bbc
6 changed files with 42 additions and 28 deletions
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7
src/main/scala/rocket/rocket.scala
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@ -6,7 +6,7 @@ import Chisel._
import uncore.devices._
import uncore.agents.CacheName
import uncore.constants._
import junctions.HasAddrMapParameters
import uncore.tilelink2._
import util._
import Chisel.ImplicitConversions._
import config._
@ -32,12 +32,14 @@ case object NBreakpoints extends Field[Int]
case object NPerfCounters extends Field[Int]
case object NPerfEvents extends Field[Int]
case object DataScratchpadSize extends Field[Int]
case object TLCacheEdge extends Field[TLEdgeOut]
trait HasCoreParameters extends HasAddrMapParameters {
trait HasCoreParameters {
implicit val p: Parameters
val xLen = p(XLen)
val fLen = xLen // TODO relax this
val edge = p(TLCacheEdge)
val usingVM = p(UseVM)
val usingUser = p(UseUser) || usingVM
val usingDebug = p(UseDebug)
@ -67,6 +69,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
def pgIdxBits = 12
def pgLevelBits = 10 - log2Ceil(xLen / 32)
def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
val paddrBits = edge.bundle.addressBits
def ppnBits = paddrBits - pgIdxBits
def vpnBits = vaddrBits - pgIdxBits
val pgLevels = p(PgLevels)