riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

[tl2] expand firstlast api and L1WB bugfix

Browse Source
This commit is contained in:
Henry Cook
2016-11-14 11:56:48 -08:00
parent b7730d66f2
commit c0efd247b0
8 changed files with 49 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/uncore/tilelink2/Fuzzer.scala
View File

@ -113,12 +113,10 @@ class TLFuzzer(
// Progress within each operation
val a = out.a.bits
val (a_first, a_last, _) = edge.firstlast(out.a)
val req_done = out.a.fire() && a_last
val (a_first, a_last, req_done) = edge.firstlast(out.a)
val d = out.d.bits
val (d_first, d_last, _) = edge.firstlast(out.d)
val resp_done = out.d.fire() && d_last
val (d_first, d_last, resp_done) = edge.firstlast(out.d)
// Source ID generation
val idMap = Module(new IDMapGenerator(inFlight))