[tl2] expand firstlast api and L1WB bugfix
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@ -175,19 +175,43 @@ class TLEdge(
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}
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}
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def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, UInt) = {
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def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
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val beats1 = numBeats1(bits)
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val counter = RegInit(UInt(0, width = log2Up(maxTransfer / manager.beatBytes)))
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val counter1 = counter - UInt(1)
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val first = counter === UInt(0)
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val last = counter === UInt(1) || beats1 === UInt(0)
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val done = last && fire
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val count = (beats1 & ~counter1)
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when (fire) {
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counter := Mux(first, beats1, counter1)
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}
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(first, last, (beats1 & ~counter1) << log2Ceil(manager.beatBytes))
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(first, last, done, count)
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}
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def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, UInt) = firstlast(x.bits, x.fire())
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def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
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def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire())
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def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
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def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire())
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def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
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val r = firstlastHelper(bits, fire)
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(r._1, r._2, r._3)
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}
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def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire())
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def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
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val r = firstlastHelper(bits, fire)
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(r._1, r._2, r._3, r._4)
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}
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def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire())
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def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
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val r = firstlastHelper(bits, fire)
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(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
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}
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def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire())
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}
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class TLEdgeOut(
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