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[tl2] expand firstlast api and L1WB bugfix

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This commit is contained in:
Henry Cook
2016-11-14 11:56:48 -08:00
parent b7730d66f2
commit c0efd247b0
8 changed files with 49 additions and 30 deletions
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2
src/main/scala/uncore/axi4/ToTL.scala
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@ -102,7 +102,7 @@ class AXI4ToTL extends LazyModule
val d_resp = Mux(out.d.bits.error, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val d_hasData = edgeOut.hasData(out.d.bits)
val (_, d_last, _) = edgeOut.firstlast(out.d.bits, out.d.fire())
val d_last = edgeOut.last(out.d)
out.d.ready := Mux(d_hasData, ok_r.ready, ok_b.ready)
ok_r.valid := out.d.valid && d_hasData